coresight: etm4x: Modify core-commit to avoid HiSilicon ETM overflow

mainline inclusion
from mainline-v5.11-rc1
commit e7255092
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I4UA33
CVE: NA

Reference: https://lore.kernel.org/r/20201208182651.1597945-4-mathieu.poirier@linaro.org



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The ETM device can't keep up with the core pipeline when cpu core
is at full speed. This may cause overflow within core and its ETM.
This is a common phenomenon on ETM devices.

On HiSilicon Hip08 platform, a specific feature is added to set
core pipeline. So commit rate can be reduced manually to avoid ETM
overflow.

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Qi Liu <liuqi115@huawei.com>
[Modified changelog title and Kconfig description]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20201208182651.1597945-4-mathieu.poirier@linaro.org


Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Qi Liu <liuqi115@huawei.com>
Reviewed-by: Jay Fang <f.fangjian@huawei.com>
Acked-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>