Commit c2910c00 authored Oct 11, 2021 by Claudiu Beznea Committed by Stephen Boyd Oct 26, 2021

clk: at91: clk-master: check if div or pres is zero

Check if div or pres is zero before using it as argument for ffs().
In case div is zero ffs() will return 0 and thus substracting from
zero will lead to invalid values to be setup in registers.

Fixes: 7a110b91 ("clk: at91: clk-master: re-factor master clock")
Fixes: 75c88143 ("clk: at91: clk-master: add master clock support for SAMA7G5")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent f12d028b

drivers/clk/at91/clk-master.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,

	else if (pres == 3)		else if (pres == 3)
	pres = MASTER_PRES_MAX;		pres = MASTER_PRES_MAX;
	else		else if (pres)
	pres = ffs(pres) - 1;		pres = ffs(pres) - 1;

	spin_lock_irqsave(master->lock, flags);		spin_lock_irqsave(master->lock, flags);
	@@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,

	if (div == 3)		if (div == 3)
	div = MASTER_PRES_MAX;		div = MASTER_PRES_MAX;
	else		else if (div)
	div = ffs(div) - 1;		div = ffs(div) - 1;

	spin_lock_irqsave(master->lock, flags);		spin_lock_irqsave(master->lock, flags);