Commit f12d028b authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Stephen Boyd
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clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL 



Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate
computed in sam9x60_frac_pll_recalc_rate() and the one computed in
sam9x60_frac_pll_compute_mul_frac().

Fixes: 43b1bb4a ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-8-claudiu.beznea@microchip.com


Acked-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 5df4cd90

drivers/clk/at91/clk-sam9x60-pll.c

+2 −2
Original line number Diff line number Diff line
@@ -73,8 +73,8 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw, 
	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);

	struct sam9x60_frac *frac = to_sam9x60_frac(core);



	return (parent_rate * (frac->mul + 1) +

		((u64)parent_rate * frac->frac >> 22));

	return parent_rate * (frac->mul + 1) +

		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));

}



static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)