Commit c1ab64aa authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom-qmp-usb: define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME register 



Other PHYs tables directly reference QPHY_PLL_LOCK_CHK_DLY_TIME register
without using reglayout. Define corresponding register to be used by
msm8996 PHY tables and use it directly.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-29-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent d36e341a

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+0 −1
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ enum qphy_reg_layout { 
	QPHY_COM_START_CONTROL,

	QPHY_COM_PCS_READY_STATUS,

	/* PCS registers */

	QPHY_PLL_LOCK_CHK_DLY_TIME,

	QPHY_SW_RESET,

	QPHY_START_CTRL,

	QPHY_PCS_READY_STATUS,

drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c

+1 −3
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ enum qphy_reg_layout { 
	QPHY_COM_START_CONTROL,

	QPHY_COM_PCS_READY_STATUS,

	/* PCS registers */

	QPHY_PLL_LOCK_CHK_DLY_TIME,

	QPHY_SW_RESET,

	QPHY_START_CTRL,

	QPHY_PCS_READY_STATUS,
@@ -141,7 +140,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_POWER_DOWN_CONTROL]	= 0x404,

	[QPHY_COM_START_CONTROL]	= 0x408,

	[QPHY_COM_PCS_READY_STATUS]	= 0x448,

	[QPHY_PLL_LOCK_CHK_DLY_TIME]	= 0xa8,

	[QPHY_SW_RESET]			= 0x00,

	[QPHY_START_CTRL]		= 0x08,

	[QPHY_PCS_STATUS]		= 0x174,
@@ -216,7 +214,7 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),



	QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05),



	QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+1 −3
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ enum qphy_reg_layout { 
	QPHY_COM_START_CONTROL,

	QPHY_COM_PCS_READY_STATUS,

	/* PCS registers */

	QPHY_PLL_LOCK_CHK_DLY_TIME,

	QPHY_SW_RESET,

	QPHY_START_CTRL,

	QPHY_PCS_READY_STATUS,
@@ -148,7 +147,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_POWER_DOWN_CONTROL]	= 0x404,

	[QPHY_COM_START_CONTROL]	= 0x408,

	[QPHY_COM_PCS_READY_STATUS]	= 0x448,

	[QPHY_PLL_LOCK_CHK_DLY_TIME]	= 0xa8,

	[QPHY_SW_RESET]			= 0x00,

	[QPHY_START_CTRL]		= 0x08,

	[QPHY_PCS_STATUS]		= 0x174,
@@ -435,7 +433,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),

	QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3			0x088

#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x0a0

#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK		0x0a4

#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME		0x0a8

#define QPHY_V2_PCS_FLL_CNTRL1				0x0c0

#define QPHY_V2_PCS_FLL_CNTRL2				0x0c4

#define QPHY_V2_PCS_FLL_CNT_VAL_L			0x0c8

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+0 −1
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ enum qphy_reg_layout { 
	QPHY_COM_START_CONTROL,

	QPHY_COM_PCS_READY_STATUS,

	/* PCS registers */

	QPHY_PLL_LOCK_CHK_DLY_TIME,

	QPHY_SW_RESET,

	QPHY_START_CTRL,

	QPHY_PCS_READY_STATUS,