Commit d36e341a authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
Browse files

phy: qcom-qmp-usb: replace FLL layout writes for msm8996 



Other PHYs tables directly reference FLL registers without using
reglayout. Define corresponding registers to be used by msm8996 PHY
tables and use them directly.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-28-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 9f2fd65f

drivers/phy/qualcomm/phy-qcom-qmp-combo.c

+0 −5
Original line number Diff line number Diff line
@@ -122,11 +122,6 @@ enum qphy_reg_layout { 
	QPHY_COM_PCS_READY_STATUS,

	/* PCS registers */

	QPHY_PLL_LOCK_CHK_DLY_TIME,

	QPHY_FLL_CNTRL1,

	QPHY_FLL_CNTRL2,

	QPHY_FLL_CNT_VAL_L,

	QPHY_FLL_CNT_VAL_H_TOL,

	QPHY_FLL_MAN_CODE,

	QPHY_SW_RESET,

	QPHY_START_CTRL,

	QPHY_PCS_READY_STATUS,

drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c

+0 −10
Original line number Diff line number Diff line
@@ -122,11 +122,6 @@ enum qphy_reg_layout { 
	QPHY_COM_PCS_READY_STATUS,

	/* PCS registers */

	QPHY_PLL_LOCK_CHK_DLY_TIME,

	QPHY_FLL_CNTRL1,

	QPHY_FLL_CNTRL2,

	QPHY_FLL_CNT_VAL_L,

	QPHY_FLL_CNT_VAL_H_TOL,

	QPHY_FLL_MAN_CODE,

	QPHY_SW_RESET,

	QPHY_START_CTRL,

	QPHY_PCS_READY_STATUS,
@@ -147,11 +142,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_START_CONTROL]	= 0x408,

	[QPHY_COM_PCS_READY_STATUS]	= 0x448,

	[QPHY_PLL_LOCK_CHK_DLY_TIME]	= 0xa8,

	[QPHY_FLL_CNTRL1]		= 0xc4,

	[QPHY_FLL_CNTRL2]		= 0xc8,

	[QPHY_FLL_CNT_VAL_L]		= 0xcc,

	[QPHY_FLL_CNT_VAL_H_TOL]	= 0xd0,

	[QPHY_FLL_MAN_CODE]		= 0xd4,

	[QPHY_SW_RESET]			= 0x00,

	[QPHY_START_CTRL]		= 0x08,

	[QPHY_PCS_STATUS]		= 0x174,

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

+0 −10
Original line number Diff line number Diff line
@@ -122,11 +122,6 @@ enum qphy_reg_layout { 
	QPHY_COM_PCS_READY_STATUS,

	/* PCS registers */

	QPHY_PLL_LOCK_CHK_DLY_TIME,

	QPHY_FLL_CNTRL1,

	QPHY_FLL_CNTRL2,

	QPHY_FLL_CNT_VAL_L,

	QPHY_FLL_CNT_VAL_H_TOL,

	QPHY_FLL_MAN_CODE,

	QPHY_SW_RESET,

	QPHY_START_CTRL,

	QPHY_PCS_READY_STATUS,
@@ -154,11 +149,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_COM_START_CONTROL]	= 0x408,

	[QPHY_COM_PCS_READY_STATUS]	= 0x448,

	[QPHY_PLL_LOCK_CHK_DLY_TIME]	= 0xa8,

	[QPHY_FLL_CNTRL1]		= 0xc4,

	[QPHY_FLL_CNTRL2]		= 0xc8,

	[QPHY_FLL_CNT_VAL_L]		= 0xcc,

	[QPHY_FLL_CNT_VAL_H_TOL]	= 0xd0,

	[QPHY_FLL_MAN_CODE]		= 0xd4,

	[QPHY_SW_RESET]			= 0x00,

	[QPHY_START_CTRL]		= 0x08,

	[QPHY_PCS_STATUS]		= 0x174,

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h

+7 −0
Original line number Diff line number Diff line
@@ -24,6 +24,13 @@ 
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3			0x088

#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x0a0

#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK		0x0a4

#define QPHY_V2_PCS_FLL_CNTRL1				0x0c0

#define QPHY_V2_PCS_FLL_CNTRL2				0x0c4

#define QPHY_V2_PCS_FLL_CNT_VAL_L			0x0c8

#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL			0x0cc

#define QPHY_V2_PCS_FLL_MAN_CODE			0x0d0



/* UFS only ? */

#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP	0x0cc

#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL			0x13c

#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME			0x140

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+0 −5
Original line number Diff line number Diff line
@@ -122,11 +122,6 @@ enum qphy_reg_layout { 
	QPHY_COM_PCS_READY_STATUS,

	/* PCS registers */

	QPHY_PLL_LOCK_CHK_DLY_TIME,

	QPHY_FLL_CNTRL1,

	QPHY_FLL_CNTRL2,

	QPHY_FLL_CNT_VAL_L,

	QPHY_FLL_CNT_VAL_H_TOL,

	QPHY_FLL_MAN_CODE,

	QPHY_SW_RESET,

	QPHY_START_CTRL,

	QPHY_PCS_READY_STATUS,