Commit c04881e8 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/aardvark' 

- Decode PIO Posted/Non-posted Request correctly in error logging (Pali
  Rohár)

- Work around incorrect Vendor ID in Marvell Armada 3700 (Pali Rohár)

* remotes/lorenzo/pci/aardvark:
  PCI: aardvark: Implement workaround for the readback value of VEND_ID
  PCI: aardvark: Fix checking for PIO Non-posted Request
parents 4343292f 7f71a409

drivers/pci/controller/pci-aardvark.c

+12 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ 
#define   PIO_COMPLETION_STATUS_UR		1

#define   PIO_COMPLETION_STATUS_CRS		2

#define   PIO_COMPLETION_STATUS_CA		4

#define   PIO_NON_POSTED_REQ			BIT(0)

#define   PIO_NON_POSTED_REQ			BIT(10)

#define PIO_ADDR_LS				(PIO_BASE_ADDR + 0x8)

#define PIO_ADDR_MS				(PIO_BASE_ADDR + 0xc)

#define PIO_WR_DATA				(PIO_BASE_ADDR + 0x10)
@@ -125,6 +125,7 @@ 
#define     LTSSM_MASK				0x3f

#define     LTSSM_L0				0x10

#define     RC_BAR_CONFIG			0x300

#define VENDOR_ID_REG				(LMI_BASE_ADDR + 0x44)



/* PCIe core controller registers */

#define CTRL_CORE_BASE_ADDR			0x18000
@@ -385,6 +386,16 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) 
	reg |= (IS_RC_MSK << IS_RC_SHIFT);

	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);



	/*

	 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.

	 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor

	 * id in high 16 bits. Updating this register changes readback value of

	 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround

	 * for erratum 4.1: "The value of device and vendor ID is incorrect".

	 */

	reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;

	advk_writel(pcie, reg, VENDOR_ID_REG);



	/* Set Advanced Error Capabilities and Control PF0 register */

	reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |

		PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |