Commit bf68dabf authored May 07, 2024 by Frank Li Committed by Ma Wupeng May 07, 2024

arm64: dts: imx8-ss-lsio: fix pwm lpcg indices

stable inclusion
from stable-v6.6.28
commit e9e44fc88abadc52ca6b0f1f8307e6967ddbec22
bugzilla: https://gitee.com/openeuler/kernel/issues/I9MPZ8

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=e9e44fc88abadc52ca6b0f1f8307e6967ddbec22



--------------------------------

commit 1d86c2b3946e69d6b0b93568d312aae6247847c0 upstream.

lpcg's arg0 should use clock indices instead of index.

pwm0_lpcg: clock-controller@5d400000 {
	...                                                // Col1  Col2
	clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,  // 0     0
		 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,  // 1     1
		 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>,  // 2     4
		 <&lsio_bus_clk>,                          // 3     5
		 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;  // 4     6
	clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
			<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
			<IMX_LPCG_CLK_6>;
};

Col1: index, which existing dts try to get.
Col2: actual index in lpcg driver.

pwm1 {
	....
	clocks = <&pwm1_lpcg 4>, <&pwm1_lpcg 1>;
                             ^^              ^^
should be:

	clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>, <&pwm1_lpcg IMX_LPCG_CLK_1>;
};

Arg0 is divided by 4 in lpcg driver, so index 0 and 1 will be get by pwm
driver, which are same as IMX_LPCG_CLK_6 and IMX_LPCG_CLK_1. Even it can
work, but code logic is wrong. Fixed it by use correct indices.

Cc: stable@vger.kernel.org
Fixes: 23fa99b2 ("arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: ZhangPeng <zhangpeng362@huawei.com>

parent 65a97a00

arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi

+8 −8

Original line number	Diff line number	Diff line
		@@ -32,8 +32,8 @@ lsio_subsys: bus@5d000000 {
		compatible = "fsl,imx27-pwm";
		reg = <0x5d000000 0x10000>;
		clock-names = "ipg", "per";
		clocks = <&pwm0_lpcg 4>,
		<&pwm0_lpcg 1>;
		clocks = <&pwm0_lpcg IMX_LPCG_CLK_6>,
		<&pwm0_lpcg IMX_LPCG_CLK_1>;
		assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <3>;
		@@ -45,8 +45,8 @@ lsio_subsys: bus@5d000000 {
		compatible = "fsl,imx27-pwm";
		reg = <0x5d010000 0x10000>;
		clock-names = "ipg", "per";
		clocks = <&pwm1_lpcg 4>,
		<&pwm1_lpcg 1>;
		clocks = <&pwm1_lpcg IMX_LPCG_CLK_6>,
		<&pwm1_lpcg IMX_LPCG_CLK_1>;
		assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <3>;
		@@ -58,8 +58,8 @@ lsio_subsys: bus@5d000000 {
		compatible = "fsl,imx27-pwm";
		reg = <0x5d020000 0x10000>;
		clock-names = "ipg", "per";
		clocks = <&pwm2_lpcg 4>,
		<&pwm2_lpcg 1>;
		clocks = <&pwm2_lpcg IMX_LPCG_CLK_6>,
		<&pwm2_lpcg IMX_LPCG_CLK_1>;
		assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <3>;
		@@ -71,8 +71,8 @@ lsio_subsys: bus@5d000000 {
		compatible = "fsl,imx27-pwm";
		reg = <0x5d030000 0x10000>;
		clock-names = "ipg", "per";
		clocks = <&pwm3_lpcg 4>,
		<&pwm3_lpcg 1>;
		clocks = <&pwm3_lpcg IMX_LPCG_CLK_6>,
		<&pwm3_lpcg IMX_LPCG_CLK_1>;
		assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <24000000>;
		#pwm-cells = <3>;