perf: hisi: Add support for HiSilicon SoC LPDDRC PMU driver

ascend inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I4D4WR


CVE: NA

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This patch adds support for LPDDRC PMU driver in HiSilicon SoC chip, Each
DDRC has own control, counter registers be an separate PMU. For each
LPDDRC PMU, it has 8-fixed-purpose counters which have been
mapped to 8-events by hardware, it assumes that counter index is equal
to event code (0 - 7) in LPDDRC PMU driver. Since the counter register
was read-only, set the perv-count in write_counter instead of wrote the
counter register.

Signed-off-by: Fang Lijun <fanglijun3@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>