Commit be3a3409 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add convert for new gfx type 



Add convert for CP RS64 related gfx ip type.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a32fa029

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+33 −0
Original line number Diff line number Diff line
@@ -2211,6 +2211,39 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 
	case AMDGPU_UCODE_ID_IMU_D:

		*type = GFX_FW_TYPE_IMU_D;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_PFP:

		*type = GFX_FW_TYPE_RS64_PFP;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_ME:

		*type = GFX_FW_TYPE_RS64_ME;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_MEC:

		*type = GFX_FW_TYPE_RS64_MEC;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:

		*type = GFX_FW_TYPE_RS64_PFP_P0_STACK;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:

		*type = GFX_FW_TYPE_RS64_PFP_P1_STACK;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:

		*type = GFX_FW_TYPE_RS64_ME_P0_STACK;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:

		*type = GFX_FW_TYPE_RS64_ME_P1_STACK;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:

		*type = GFX_FW_TYPE_RS64_MEC_P0_STACK;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:

		*type = GFX_FW_TYPE_RS64_MEC_P1_STACK;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:

		*type = GFX_FW_TYPE_RS64_MEC_P2_STACK;

		break;

	case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:

		*type = GFX_FW_TYPE_RS64_MEC_P3_STACK;

		break;

	case AMDGPU_UCODE_ID_MAXIMUM:

	default:

		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

+11 −0
Original line number Diff line number Diff line
@@ -389,6 +389,17 @@ enum AMDGPU_UCODE_ID { 
	AMDGPU_UCODE_ID_CP_CE,

	AMDGPU_UCODE_ID_CP_PFP,

	AMDGPU_UCODE_ID_CP_ME,

	AMDGPU_UCODE_ID_CP_RS64_PFP,

	AMDGPU_UCODE_ID_CP_RS64_ME,

	AMDGPU_UCODE_ID_CP_RS64_MEC,

	AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,

	AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,

	AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,

	AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,

	AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,

	AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,

	AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,

	AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,

	AMDGPU_UCODE_ID_CP_MEC1,

	AMDGPU_UCODE_ID_CP_MEC1_JT,

	AMDGPU_UCODE_ID_CP_MEC2,