Commit bc4fac42 authored by Pali Rohár's avatar Pali Rohár Committed by Lorenzo Pieralisi
Browse files

PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge 

Aardvark supports PCIe Hot Reset via PCIE_CORE_CTRL1_REG.

Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL
register on emulated bridge.

With this, the function pci_reset_secondary_bus() starts working and can
reset connected PCIe card. Custom userspace script [1] which uses setpci
can trigger PCIe Hot Reset and reset the card manually.

[1] https://alexforencich.com/wiki/en/pcie/hot-reset-linux

Link: https://lore.kernel.org/r/20211028185659.20329-7-kabel@kernel.org


Fixes: 8a3ebd8d ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
parent 84e1b404

drivers/pci/controller/pci-aardvark.c

+27 −0
Original line number Diff line number Diff line
@@ -773,6 +773,22 @@ advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, 
		*value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);

		return PCI_BRIDGE_EMUL_HANDLED;



	case PCI_INTERRUPT_LINE: {

		/*

		 * From the whole 32bit register we support reading from HW only

		 * one bit: PCI_BRIDGE_CTL_BUS_RESET.

		 * Other bits are retrieved only from emulated config buffer.

		 */

		__le32 *cfgspace = (__le32 *)&bridge->conf;

		u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);

		if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)

			val |= PCI_BRIDGE_CTL_BUS_RESET << 16;

		else

			val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);

		*value = val;

		return PCI_BRIDGE_EMUL_HANDLED;

	}



	default:

		return PCI_BRIDGE_EMUL_NOT_HANDLED;

	}
@@ -789,6 +805,17 @@ advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, 
		advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);

		break;



	case PCI_INTERRUPT_LINE:

		if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {

			u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);

			if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))

				val |= HOT_RESET_GEN;

			else

				val &= ~HOT_RESET_GEN;

			advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);

		}

		break;



	default:

		break;

	}