Commit 84e1b404 authored by Pali Rohár's avatar Pali Rohár Committed by Lorenzo Pieralisi
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PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge 

Aardvark controller has something like config space of a Root Port
available at offset 0x0 of internal registers - these registers are used
for implementation of the emulated bridge.

The default value of Class Code of this bridge corresponds to a RAID Mass
storage controller, though. (This is probably intended for when the
controller is used as Endpoint.)

Change the Class Code to correspond to a PCI Bridge.

Add comment explaining this change.

Link: https://lore.kernel.org/r/20211028185659.20329-6-kabel@kernel.org


Fixes: 8a3ebd8d ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Signed-off-by: default avatarMarek Behún <kabel@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org
parent 771153fc

drivers/pci/controller/pci-aardvark.c

+20 −0
Original line number Diff line number Diff line
@@ -511,6 +511,26 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) 
	reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;

	advk_writel(pcie, reg, VENDOR_ID_REG);



	/*

	 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),

	 * because the default value is Mass storage controller (0x010400).

	 *

	 * Note that this Aardvark PCI Bridge does not have compliant Type 1

	 * Configuration Space and it even cannot be accessed via Aardvark's

	 * PCI config space access method. Something like config space is

	 * available in internal Aardvark registers starting at offset 0x0

	 * and is reported as Type 0. In range 0x10 - 0x34 it has totally

	 * different registers.

	 *

	 * Therefore driver uses emulation of PCI Bridge which emulates

	 * access to configuration space via internal Aardvark registers or

	 * emulated configuration buffer.

	 */

	reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);

	reg &= ~0xffffff00;

	reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;

	advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);



	/* Disable Root Bridge I/O space, memory space and bus mastering */

	reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);

	reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);