Commit bbc3b403 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-imx', 'clk-samsung', 'clk-zynq', 'clk-rockchip' and... 

Merge branches 'clk-imx', 'clk-samsung', 'clk-zynq', 'clk-rockchip' and 'clk-uniphier' into clk-next

 - Simplify Zynq Kconfig dependencies

* clk-imx:
  clk: imx: Reference preceded by free
  clk: imx8mq: Correct the pcie1 sels
  clk: imx8mp: Remove the none exist pcie clocks
  clk: imx: Fix reparenting of UARTs not associated with stdout

* clk-samsung:
  clk: samsung: Remove redundant dev_err calls
  clk: exynos7: Mark aclk_fsys1_200 as critical

* clk-zynq:
  clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable
  clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
  clk: zynqmp: Drop dependency on ARCH_ZYNQMP
  clk: zynqmp: Enable the driver if ZYNQMP_FIRMWARE is selected

* clk-rockchip:
  clk: rockchip: drop MODULE_ALIAS from rk3399 clock controller
  clk: rockchip: drop parenthesis from ARM || COMPILE_TEST depends
  clk: rockchip: add clock controller for rk3568
  clk: rockchip: support more core div setting
  dt-binding: clock: Document rockchip, rk3568-cru bindings
  clk: rockchip: add dt-binding header for rk3568

* clk-uniphier:
  clk: uniphier: Fix potential infinite loop
parents c3ad3219 5c55197c fdac035e 394cdb69 89bf9bb7 f6b1340d

Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml

0 → 100644
+60 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ROCKCHIP rk3568 Family Clock Control Module Binding



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description: |

  The RK3568 clock controller generates the clock and also implements a

  reset controller for SoC peripherals.

  (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)

  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All available clocks are defined as

  preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be

  used in device tree sources.



properties:

  compatible:

    enum:

      - rockchip,rk3568-cru

      - rockchip,rk3568-pmucru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  # Clock Control Module node:

  - |

    pmucru: clock-controller@fdd00000 {

      compatible = "rockchip,rk3568-pmucru";

      reg = <0xfdd00000 0x1000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

  - |

    cru: clock-controller@fdd20000 {

      compatible = "rockchip,rk3568-cru";

      reg = <0xfdd20000 0x1000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

drivers/clk/imx/clk-imx25.c

+1 −11
Original line number Diff line number Diff line
@@ -73,16 +73,6 @@ enum mx25_clks { 


static struct clk *clk[clk_max];



static struct clk ** const uart_clks[] __initconst = {

	&clk[uart_ipg_per],

	&clk[uart1_ipg],

	&clk[uart2_ipg],

	&clk[uart3_ipg],

	&clk[uart4_ipg],

	&clk[uart5_ipg],

	NULL

};



static int __init __mx25_clocks_init(void __iomem *ccm_base)

{

	BUG_ON(!ccm_base);
@@ -228,7 +218,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base) 
	 */

	clk_set_parent(clk[cko_sel], clk[ipg]);



	imx_register_uart_clocks(uart_clks);

	imx_register_uart_clocks(6);



	return 0;

}

drivers/clk/imx/clk-imx27.c

+1 −12
Original line number Diff line number Diff line
@@ -49,17 +49,6 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; 
static struct clk *clk[IMX27_CLK_MAX];

static struct clk_onecell_data clk_data;



static struct clk ** const uart_clks[] __initconst = {

	&clk[IMX27_CLK_PER1_GATE],

	&clk[IMX27_CLK_UART1_IPG_GATE],

	&clk[IMX27_CLK_UART2_IPG_GATE],

	&clk[IMX27_CLK_UART3_IPG_GATE],

	&clk[IMX27_CLK_UART4_IPG_GATE],

	&clk[IMX27_CLK_UART5_IPG_GATE],

	&clk[IMX27_CLK_UART6_IPG_GATE],

	NULL

};



static void __init _mx27_clocks_init(unsigned long fref)

{

	BUG_ON(!ccm);
@@ -176,7 +165,7 @@ static void __init _mx27_clocks_init(unsigned long fref) 


	clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);



	imx_register_uart_clocks(uart_clks);

	imx_register_uart_clocks(7);



	imx_print_silicon_rev("i.MX27", mx27_revision());

}

drivers/clk/imx/clk-imx35.c

+1 −9
Original line number Diff line number Diff line
@@ -82,14 +82,6 @@ enum mx35_clks { 


static struct clk *clk[clk_max];



static struct clk ** const uart_clks[] __initconst = {

	&clk[ipg],

	&clk[uart1_gate],

	&clk[uart2_gate],

	&clk[uart3_gate],

	NULL

};



static void __init _mx35_clocks_init(void)

{

	void __iomem *base;
@@ -243,7 +235,7 @@ static void __init _mx35_clocks_init(void) 
	 */

	clk_prepare_enable(clk[scc_gate]);



	imx_register_uart_clocks(uart_clks);

	imx_register_uart_clocks(4);



	imx_print_silicon_rev("i.MX35", mx35_revision());

}

drivers/clk/imx/clk-imx5.c

+3 −27
Original line number Diff line number Diff line
@@ -128,30 +128,6 @@ static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_ 
static struct clk *clk[IMX5_CLK_END];

static struct clk_onecell_data clk_data;



static struct clk ** const uart_clks_mx51[] __initconst = {

	&clk[IMX5_CLK_UART1_IPG_GATE],

	&clk[IMX5_CLK_UART1_PER_GATE],

	&clk[IMX5_CLK_UART2_IPG_GATE],

	&clk[IMX5_CLK_UART2_PER_GATE],

	&clk[IMX5_CLK_UART3_IPG_GATE],

	&clk[IMX5_CLK_UART3_PER_GATE],

	NULL

};



static struct clk ** const uart_clks_mx50_mx53[] __initconst = {

	&clk[IMX5_CLK_UART1_IPG_GATE],

	&clk[IMX5_CLK_UART1_PER_GATE],

	&clk[IMX5_CLK_UART2_IPG_GATE],

	&clk[IMX5_CLK_UART2_PER_GATE],

	&clk[IMX5_CLK_UART3_IPG_GATE],

	&clk[IMX5_CLK_UART3_PER_GATE],

	&clk[IMX5_CLK_UART4_IPG_GATE],

	&clk[IMX5_CLK_UART4_PER_GATE],

	&clk[IMX5_CLK_UART5_IPG_GATE],

	&clk[IMX5_CLK_UART5_PER_GATE],

	NULL

};



static void __init mx5_clocks_common_init(void __iomem *ccm_base)

{

	clk[IMX5_CLK_DUMMY]		= imx_clk_fixed("dummy", 0);
@@ -382,7 +358,7 @@ static void __init mx50_clocks_init(struct device_node *np) 
	r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);

	clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);



	imx_register_uart_clocks(uart_clks_mx50_mx53);

	imx_register_uart_clocks(5);

}

CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
@@ -488,7 +464,7 @@ static void __init mx51_clocks_init(struct device_node *np) 
	val |= 1 << 23;

	writel(val, MXC_CCM_CLPCR);



	imx_register_uart_clocks(uart_clks_mx51);

	imx_register_uart_clocks(3);

}

CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
@@ -633,6 +609,6 @@ static void __init mx53_clocks_init(struct device_node *np) 
	r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);

	clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);



	imx_register_uart_clocks(uart_clks_mx50_mx53);

	imx_register_uart_clocks(5);

}

CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);