Commit c3ad3219 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner'... 

Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and 'clk-qcom' into clk-next

 - Use clk_hw pointers in socfpga driver
 - Cleanup parent data in qcom clk drivers

* clk-cleanup:
  clk: Drop double "if" in clk_core_determine_round_nolock() comment
  clk: at91: Trivial typo fixes in the file sama7g5.c
  clk: use clk_core_enable_lock() a bit more

* clk-renesas:
  clk: renesas: Zero init clk_init_data
  clk: renesas: Couple of spelling fixes
  clk: renesas: r8a779a0: Add CMT clocks
  clk: renesas: r8a7795: Add TMU clocks
  clk: renesas: r8a779a0: Add TSC clock
  clk: renesas: r8a779a0: Add TMU clocks
  clk: renesas: r8a77965: Add DAB clock
  clk: renesas: r8a77990: Add DAB clock

* clk-socfpga:
  clk: socfpga: remove redundant initialization of variable div
  clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return
  clk: socfpga: Fix code formatting
  clk: socfpga: Convert to s10/agilex/n5x to use clk_hw
  clk: socfpga: arria10: convert to use clk_hw
  clk: socfpga: use clk_hw_register for a5/c5

* clk-allwinner:
  clk: sunxi: Demote non-conformant kernel-doc headers
  clk: sunxi-ng: v3s: use sigma-delta modulation for audio-pll

* clk-qcom: (45 commits)
  clk: qcom: rpmh: add support for SDX55 rpmh IPA clock
  clk: qcom: gcc-sdm845: get rid of the test clock
  clk: qcom: convert SDM845 Global Clock Controller to parent_data
  dt-bindings: clock: separate SDM845 GCC clock bindings
  clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: a7-pll: Add missing MODULE_DEVICE_TABLE
  clk: qcom: gcc-sm8350: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-sm8250: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-sc8180x: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-sc7180: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: videocc-sm8250: use parent_hws where possible
  clk: qcom: videocc-sm8150: use parent_hws where possible
  clk: qcom: gpucc-sm8250: use parent_hws where possible
  clk: qcom: gpucc-sm8150: use parent_hws where possible
  clk: qcom: gcc-sm8350: use parent_hws where possible
  clk: qcom: gcc-sm8250: use parent_hws where possible
  clk: qcom: gcc-sm8150: use parent_hws where possible
  clk: qcom: gcc-sdx55: use parent_hws where possible
  ...
parents e27453ad 3338fe50 52d1a8da 7c09e605 b2150cab

Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml

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# SPDX-License-Identifier: GPL-2.0-only

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding



maintainers:

  - Stephen Boyd <sboyd@kernel.org>

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SDM845



  See also:

  - dt-bindings/clock/qcom,gcc-sdm845.h



properties:

  compatible:

    const: qcom,gcc-sdm845



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source

      - description: PCIE 0 Pipe clock source

      - description: PCIE 1 Pipe clock source



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk

      - const: pcie_0_pipe_clk

      - const: pcie_1_pipe_clk



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



  protected-clocks:

    description:

      Protected clock specifier list as per common clock binding.



required:

  - compatible

  - reg

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  # Example for GCC for SDM845:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sdm845";

      reg = <0x100000 0x1f0000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>,

               <&pcie0_lane>,

               <&pcie1_lane>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc.yaml

+0 −2
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@@ -32,7 +32,6 @@ description: | 
  - dt-bindings/clock/qcom,gcc-mdm9615.h

  - dt-bindings/reset/qcom,gcc-mdm9615.h

  - dt-bindings/clock/qcom,gcc-sdm660.h  (qcom,gcc-sdm630 and qcom,gcc-sdm660)

  - dt-bindings/clock/qcom,gcc-sdm845.h



properties:

  compatible:
@@ -52,7 +51,6 @@ properties: 
      - qcom,gcc-mdm9615

      - qcom,gcc-sdm630

      - qcom,gcc-sdm660

      - qcom,gcc-sdm845



  '#clock-cells':

    const: 1

drivers/clk/qcom/a53-pll.c

+1 −0
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@@ -93,6 +93,7 @@ static const struct of_device_id qcom_a53pll_match_table[] = { 
	{ .compatible = "qcom,msm8916-a53pll" },

	{ }

};

MODULE_DEVICE_TABLE(of, qcom_a53pll_match_table);



static struct platform_driver qcom_a53pll_driver = {

	.probe = qcom_a53pll_probe,

drivers/clk/qcom/a7-pll.c

+1 −0
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@@ -86,6 +86,7 @@ static const struct of_device_id qcom_a7pll_match_table[] = { 
	{ .compatible = "qcom,sdx55-a7pll" },

	{ }

};

MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);



static struct platform_driver qcom_a7pll_driver = {

	.probe = qcom_a7pll_probe,

drivers/clk/qcom/apss-ipq-pll.c

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = { 
	{ .compatible = "qcom,ipq6018-a53pll" },

	{ }

};

MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);



static struct platform_driver apss_ipq_pll_driver = {

	.probe = apss_ipq_pll_probe,