Commit bb07af2e authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dsi/phy: fix 7nm v4.0 settings for C-PHY mode 



The dsi_7nm_phy_enable() disagrees with downstream for
glbl_str_swi_cal_sel_ctrl and glbl_hstx_str_ctrl_0 values. Update
programmed settings to match downstream driver. To remove the
possibility for such errors in future drop less_than_1500_mhz
assignment and specify settings explicitly.

Fixes: 5ac17838 ("drm/msm/dsi: support CPHY mode for 7nm pll/phy")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Link: https://lore.kernel.org/r/20220217000837.435340-1-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 7d8e9a90

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

+14 −8
Original line number Diff line number Diff line
@@ -864,20 +864,26 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, 
	/* Alter PHY configurations if data rate less than 1.5GHZ*/

	less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);



	/* For C-PHY, no low power settings for lower clk rate */

	if (phy->cphy_mode)

		less_than_1500_mhz = false;



	if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {

		vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;

		if (phy->cphy_mode) {

			glbl_rescode_top_ctrl = 0x00;

			glbl_rescode_bot_ctrl = 0x3c;

		} else {

			glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x00;

			glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 :  0x3c;

		}

		glbl_str_swi_cal_sel_ctrl = 0x00;

		glbl_hstx_str_ctrl_0 = 0x88;

	} else {

		vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;

		if (phy->cphy_mode) {

			glbl_str_swi_cal_sel_ctrl = 0x03;

			glbl_hstx_str_ctrl_0 = 0x66;

		} else {

			glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;

			glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;

		}

		glbl_rescode_top_ctrl = 0x03;

		glbl_rescode_bot_ctrl = 0x3c;

	}