Commit bae4de61 authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-phyboard-pollux-rdk: correct eqos pad settings 



BIT3 and BIT0 are reserved bits, should not touch.

Fixes: 6f968526 ("arm64: dts: freescale: Add support EQOS MAC on phyBOARD-Pollux-i.MX8MP")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarRasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e266c155

arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts

+14 −14
Original line number Diff line number Diff line
@@ -116,20 +116,20 @@ 
&iomuxc {

	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x3

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x3

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x91

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x91

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x91

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x91

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16

			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10

		>;

	};