Commit 6f968526 authored by Marek Vasut's avatar Marek Vasut Committed by Shawn Guo
Browse files

arm64: dts: freescale: Add support EQOS MAC on phyBOARD-Pollux-i.MX8MP 



The board has both MACs routed out, enable the EQOS.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ec4d1196

arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts

+44 −0
Original line number Diff line number Diff line
@@ -33,6 +33,30 @@ 
	};

};



&eqos {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_eqos>;

	phy-mode = "rgmii-id";

	phy-handle = <&ethphy0>;

	status = "okay";



	mdio {

		compatible = "snps,dwmac-mdio";

		#address-cells = <1>;

		#size-cells = <0>;



		ethphy0: ethernet-phy@1 {

			compatible = "ethernet-phy-ieee802.3-c22";

			reg = <0x1>;

			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;

			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;

			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;

			enet-phy-lane-no-swap;

		};

	};

};



&i2c2 {

	clock-frequency = <400000>;

	pinctrl-names = "default";
@@ -90,6 +114,26 @@ 
};



&iomuxc {

	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x3

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x3

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x91

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x91

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x91

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x91

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f

			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10

		>;

	};



	pinctrl_i2c2: i2c2grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3