Commit bac8a20f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mtd/for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 

Pull MTD updates from Miquel Raynal:
 "Core MTD changes:
   - Use refcount to prevent corruption
   - Call external _get and _put in right order
   - Fix use-after-free in mtd release
   - Explicitly include correct DT includes
   - Clean refcounting with MTD_PARTITIONED_MASTER
   - mtdblock: make warning messages ratelimited
   - dt-bindings: Add SEAMA partition bindings

  Device driver changes:
   - Use devm helper functions
   - Fix questionable cast, remove pointless ones.
   - error handling fixes
   - add support for new chip versions
   - update DT bindings
   - misc cleanups - fix typos, whitespace, indentation"

* tag 'mtd/for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (105 commits)
  dt-bindings: mtd: amlogic,meson-nand: drop unneeded quotes
  mtd: spear_smi: Use helper function devm_clk_get_enabled()
  mtd: rawnand: orion: Use helper function devm_clk_get_optional_enabled()
  mtd: rawnand: vf610_nfc: Use helper function devm_clk_get_enabled()
  mtd: rawnand: sunxi: Use helper function devm_clk_get_enabled()
  mtd: rawnand: stm32_fmc2: Use helper function devm_clk_get_enabled()
  mtd: rawnand: mtk: Use helper function devm_clk_get_enabled()
  mtd: rawnand: mpc5121: Use helper function devm_clk_get_enabled()
  mtd: rawnand: lpc32xx_slc: Use helper function devm_clk_get_enabled()
  mtd: rawnand: intel: Use helper function devm_clk_get_enabled()
  mtd: rawnand: fsmc: Use helper function devm_clk_get_enabled()
  mtd: rawnand: arasan: Use helper function devm_clk_get_enabled()
  mtd: rawnand: qcom: Add read/read_start ops in exec_op path
  mtd: rawnand: qcom: Clear buf_count and buf_start in raw read
  mtd: maps: fix -Wvoid-pointer-to-enum-cast warning
  mtd: rawnand: fix -Wvoid-pointer-to-enum-cast warning
  mtd: rawnand: fsmc: handle clk prepare error in fsmc_nand_resume()
  mtd: rawnand: Propagate error and simplify ternary operators for brcmstb_nand_wait_for_completion()
  mtd: rawnand: qcom: Sort includes alphabetically
  mtd: rawnand: qcom: Do not override the error no of submit_descs()
  ...
parents 92901222 54a3f6e8

Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml

+5 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ patternProperties: 
        const: hw



      nand-ecc-step-size:

        const: 1024

        enum: [512, 1024]



      nand-ecc-strength:

        enum: [8, 16, 24, 30, 40, 50, 60]
@@ -66,6 +66,10 @@ patternProperties: 


    unevaluatedProperties: false



    dependencies:

      nand-ecc-strength: [nand-ecc-step-size]

      nand-ecc-step-size: [nand-ecc-strength]





required:

  - compatible

Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml

+19 −2
Original line number Diff line number Diff line
@@ -43,8 +43,10 @@ properties: 
          - const: jedec,spi-nor

      - const: jedec,spi-nor

    description:

      Must also include "jedec,spi-nor" for any SPI NOR flash that can be

      identified by the JEDEC READ ID opcode (0x9F).

      SPI NOR flashes compatible with the JEDEC SFDP standard or which may be

      identified with the READ ID opcode (0x9F) do not deserve a specific

      compatible. They should instead only be matched against the generic

      "jedec,spi-nor" compatible.



  reg:

    minItems: 1
@@ -70,6 +72,21 @@ properties: 
      be used on such systems, to denote the absence of a reliable reset

      mechanism.



  no-wp:

    type: boolean

    description:

      The status register write disable (SRWD) bit in status register, combined

      with the WP# signal, provides hardware data protection for the device. When

      the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard

      strapped to LOW, the status register nonvolatile bits become read-only and

      the WRITE STATUS REGISTER operation will not execute. The only way to exit

      this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the

      flash device is not connected or is wrongly tied to GND (that includes internal

      pull-downs) then status register permanently becomes read-only as the SRWD bit

      cannot be reset. This boolean flag can be used on such systems to avoid setting

      the SRWD bit while writing the status register. WP# signal hard strapped to GND

      can be a valid use case.



  reset-gpios:

    description:

      A GPIO line connected to the RESET (active low) signal of the device.

Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ properties: 
          - const: marvell,armada-8k-nand-controller

          - const: marvell,armada370-nand-controller

      - enum:

          - marvell,ac5-nand-controller

          - marvell,armada370-nand-controller

          - marvell,pxa3xx-nand-controller

      - description: legacy bindings

Documentation/devicetree/bindings/mtd/nand-controller.yaml

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#

Documentation/devicetree/bindings/mtd/oxnas-nand.txt

deleted100644 → 0
+0 −41
Original line number Diff line number Diff line 
* Oxford Semiconductor OXNAS NAND Controller



Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.



Required properties:

 - compatible: "oxsemi,ox820-nand"

 - reg: Base address and length for NAND mapped memory.



Optional Properties:

 - clocks: phandle to the NAND gate clock if needed.

 - resets: phandle to the NAND reset control if needed.



Example:



nandc: nand-controller@41000000 {

	compatible = "oxsemi,ox820-nand";

	reg = <0x41000000 0x100000>;

	clocks = <&stdclk CLK_820_NAND>;

	resets = <&reset RESET_NAND>;

	#address-cells = <1>;

	#size-cells = <0>;



	nand@0 {

		reg = <0>;

		#address-cells = <1>;

		#size-cells = <1>;

		nand-ecc-mode = "soft";

		nand-ecc-algo = "hamming";



		partition@0 {

			label = "boot";

			reg = <0x00000000 0x00e00000>;

			read-only;

		};



		partition@e00000 {

			label = "ubi";

			reg = <0x00e00000 0x07200000>;

		};

	};

};