Commit 54a3f6e8 authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'nand/for-6.6' into mtd/next 



Raw NAND core changes:
* Fix -Wvoid-pointer-to-enum-cast warning
* Export 'nand_exit_status_op()'
* dt-bindings: Fix nand-controller.yaml license

Raw NAND controller driver changes:
* Omap, Omap2, Samsung, Atmel, fsl_upm, lpc32xx_slc, lpc32xx_mlc, STM32_FMC2,
  sh_ftlctl, MXC, Sunxi:
  - Use devm_platform_get_and_ioremap_resource()
* Orion, vf610_nfc, Sunxi, STM32_FMC2, MTK, mpc5121, lpc32xx_slc, Intel,
  FSMC, Arasan:
  - Use helper function devm_clk_get_optional_enabled()
* Brcmnand:
  - Use devm_platform_ioremap_resource_byname()
  - Propagate init error -EPROBE_DEFER up
  - Propagate error and simplify ternary operators
  - Fix mtd oobsize
  - Fix potential out-of-bounds access in oob write
  - Fix crash during the panic_write
  - Fix potential false time out warning
  - Fix ECC level field setting for v7.2 controller
* fsmc: Handle clk prepare error in fsmc_nand_resume()
* Marvell: Add support for AC5 SoC
* Meson:
  - Support for 512B ECC step size
  - Fix build error
  - Use NAND core API to check status
  - dt-bindings:
    * Make ECC properties dependent
    * Support for 512B ECC step size
    * Drop unneeded quotes
* Oxnas: Remove driver and bindings
* Qcom:
  - Conversion to ->exec_op()
  - Removal of the legacy interface
  - Two full series of improvements/misc fixes
    * Use the BIT() macro
    * Use u8 instead of uint8_t
    * Fix alignment with open parenthesis
    * Fix the spacing
    * Fix wrong indentation
    * Fix a typo
    * Early structure initialization
    * Fix address parsing within ->exec_op()
    * Remove superfluous initialization of "ret"
    * Rename variables in qcom_op_cmd_mapping()
    * Handle unsupported opcode in qcom_op_cmd_mapping()
    * Fix the opcode check in qcom_check_op()
    * Use EOPNOTSUPP instead of ENOTSUPP
    * Wrap qcom_nand_exec_op() to 80 columns
    * Unmap sg_list and free desc within submic_descs()
    * Simplify the call to nand_prog_page_end_op()
    * Do not override the error no of submit_descs()
    * Sort includes alphabetically
    * Clear buf_count and buf_start in raw read
    * Add read/read_start ops in exec_op path
* vf610_nfc: Do not check 0 for platform_get_irq()

SPI-NAND changes:
* gigadevice: Add support for GD5F1GQ{4,5}RExxH
* esmt: Add support for F50D2G41KA
* toshiba: Add support for T{C,H}58NYG{0,2}S3HBAI4 and TH58NYG3S0HBAI6

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parents 000412e4 b9283ac0

Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml

+5 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ patternProperties: 
        const: hw



      nand-ecc-step-size:

        const: 1024

        enum: [512, 1024]



      nand-ecc-strength:

        enum: [8, 16, 24, 30, 40, 50, 60]
@@ -66,6 +66,10 @@ patternProperties: 


    unevaluatedProperties: false



    dependencies:

      nand-ecc-strength: [nand-ecc-step-size]

      nand-ecc-step-size: [nand-ecc-strength]





required:

  - compatible

Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ properties: 
          - const: marvell,armada-8k-nand-controller

          - const: marvell,armada370-nand-controller

      - enum:

          - marvell,ac5-nand-controller

          - marvell,armada370-nand-controller

          - marvell,pxa3xx-nand-controller

      - description: legacy bindings

Documentation/devicetree/bindings/mtd/nand-controller.yaml

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#

Documentation/devicetree/bindings/mtd/oxnas-nand.txt

deleted100644 → 0
+0 −41
Original line number Diff line number Diff line 
* Oxford Semiconductor OXNAS NAND Controller



Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.



Required properties:

 - compatible: "oxsemi,ox820-nand"

 - reg: Base address and length for NAND mapped memory.



Optional Properties:

 - clocks: phandle to the NAND gate clock if needed.

 - resets: phandle to the NAND reset control if needed.



Example:



nandc: nand-controller@41000000 {

	compatible = "oxsemi,ox820-nand";

	reg = <0x41000000 0x100000>;

	clocks = <&stdclk CLK_820_NAND>;

	resets = <&reset RESET_NAND>;

	#address-cells = <1>;

	#size-cells = <0>;



	nand@0 {

		reg = <0>;

		#address-cells = <1>;

		#size-cells = <1>;

		nand-ecc-mode = "soft";

		nand-ecc-algo = "hamming";



		partition@0 {

			label = "boot";

			reg = <0x00000000 0x00e00000>;

			read-only;

		};



		partition@e00000 {

			label = "ubi";

			reg = <0x00e00000 0x07200000>;

		};

	};

};

drivers/mtd/nand/onenand/onenand_omap2.c

+2 −8
Original line number Diff line number Diff line
@@ -467,12 +467,6 @@ static int omap2_onenand_probe(struct platform_device *pdev) 
	struct device *dev = &pdev->dev;

	struct device_node *np = dev->of_node;



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!res) {

		dev_err(dev, "error getting memory resource\n");

		return -EINVAL;

	}



	r = of_property_read_u32(np, "reg", &val);

	if (r) {

		dev_err(dev, "reg not found in DT\n");
@@ -486,11 +480,11 @@ static int omap2_onenand_probe(struct platform_device *pdev) 
	init_completion(&c->irq_done);

	init_completion(&c->dma_done);

	c->gpmc_cs = val;

	c->phys_base = res->start;



	c->onenand.base = devm_ioremap_resource(dev, res);

	c->onenand.base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);

	if (IS_ERR(c->onenand.base))

		return PTR_ERR(c->onenand.base);

	c->phys_base = res->start;



	c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);

	if (IS_ERR(c->int_gpiod)) {