Commit ba9086a6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.9-2020-08-20' of... 

Merge tag 'amd-drm-fixes-5.9-2020-08-20' of git://people.freedesktop.org/~agd5f/linux

 into drm-fixes

amd-drm-fixes-5.9-2020-08-20:

amdgpu:
- Fixes for Navy Flounder
- Misc display fixes
- RAS fix

amdkfd:
- SDMA fix for renoir

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200820041938.3928-1-alexander.deucher@amd.com
parents 485d41b0 da2446b6

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+22 −9
Original line number Diff line number Diff line
@@ -195,19 +195,32 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 
				unsigned int engine_id,

				unsigned int queue_id)

{

	uint32_t sdma_engine_reg_base[2] = {

		SOC15_REG_OFFSET(SDMA0, 0,

				 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,

		SOC15_REG_OFFSET(SDMA1, 0,

				 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL

	};

	uint32_t retval = sdma_engine_reg_base[engine_id]

	uint32_t sdma_engine_reg_base = 0;

	uint32_t sdma_rlc_reg_offset;



	switch (engine_id) {

	default:

		dev_warn(adev->dev,

			 "Invalid sdma engine id (%d), using engine id 0\n",

			 engine_id);

		fallthrough;

	case 0:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,

				mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	case 1:

		sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,

				mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;

		break;

	}



	sdma_rlc_reg_offset = sdma_engine_reg_base

		+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);



	pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,

			queue_id, retval);

		 queue_id, sdma_rlc_reg_offset);



	return retval;

	return sdma_rlc_reg_offset;

}



static inline struct v9_mqd *get_mqd(void *mqd)

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+0 −2
Original line number Diff line number Diff line
@@ -1243,7 +1243,6 @@ void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, 
	if (!obj || !obj->ent)

		return;



	debugfs_remove(obj->ent);

	obj->ent = NULL;

	put_obj(obj);

}
@@ -1257,7 +1256,6 @@ static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) 
		amdgpu_ras_debugfs_remove(adev, &obj->head);

	}



	debugfs_remove_recursive(con->dir);

	con->dir = NULL;

}

/* debugfs end */

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+1 −2
Original line number Diff line number Diff line
@@ -179,12 +179,11 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) 
		}

		break;

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		err = psp_init_ta_microcode(&adev->psp, chip_name);

		if (err)

			return err;

		break;

	case CHIP_NAVY_FLOUNDER:

		break;

	default:

		BUG();

	}

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

+15 −1
Original line number Diff line number Diff line
@@ -1108,6 +1108,18 @@ static enum bp_result bios_parser_enable_disp_power_gating( 
		action);

}



static enum bp_result bios_parser_enable_lvtma_control(

	struct dc_bios *dcb,

	uint8_t uc_pwr_on)

{

	struct bios_parser *bp = BP_FROM_DCB(dcb);



	if (!bp->cmd_tbl.enable_lvtma_control)

		return BP_RESULT_FAILURE;



	return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on);

}



static bool bios_parser_is_accelerated_mode(

	struct dc_bios *dcb)

{
@@ -2208,7 +2220,9 @@ static const struct dc_vbios_funcs vbios_funcs = { 
	.get_board_layout_info = bios_get_board_layout_info,

	.pack_data_tables = bios_parser_pack_data_tables,



	.get_atom_dc_golden_table = bios_get_atom_dc_golden_table

	.get_atom_dc_golden_table = bios_get_atom_dc_golden_table,



	.enable_lvtma_control = bios_parser_enable_lvtma_control

};



static bool bios_parser2_construct(

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

+28 −0
Original line number Diff line number Diff line
@@ -904,6 +904,33 @@ static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id) 
	return 0;

}



/******************************************************************************

 ******************************************************************************

 **

 **                  LVTMA CONTROL

 **

 ******************************************************************************

 *****************************************************************************/



static enum bp_result enable_lvtma_control(

	struct bios_parser *bp,

	uint8_t uc_pwr_on);



static void init_enable_lvtma_control(struct bios_parser *bp)

{

	/* TODO add switch for table vrsion */

	bp->cmd_tbl.enable_lvtma_control = enable_lvtma_control;



}



static enum bp_result enable_lvtma_control(

	struct bios_parser *bp,

	uint8_t uc_pwr_on)

{

	enum bp_result result = BP_RESULT_FAILURE;

	return result;

}



void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)

{

	init_dig_encoder_control(bp);
@@ -919,4 +946,5 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp) 
	init_set_dce_clock(bp);

	init_get_smu_clock_info(bp);



	init_enable_lvtma_control(bp);

}