Commit 485d41b0 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.9-2020-08-12' of... 

Merge tag 'amd-drm-fixes-5.9-2020-08-12' of git://people.freedesktop.org/~agd5f/linux

 into drm-fixes

amd-drm-fixes-5.9-2020-08-12:

amdgpu:
- Fix allocation size
- SR-IOV fixes
- Vega20 SMU feature state caching fix
- Fix custom pptable handling
- Arcturus golden settings update
- Several display fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200813033610.4008-1-alexander.deucher@amd.com
parents f2ea2578 f41ed88c

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -462,7 +462,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 
	unsigned int pages;

	int i, r;



	*sgt = kmalloc(sizeof(*sg), GFP_KERNEL);

	*sgt = kmalloc(sizeof(**sgt), GFP_KERNEL);

	if (!*sgt)

		return -ENOMEM;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+1 −0
Original line number Diff line number Diff line
@@ -691,6 +691,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)

};



static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

+19 −0
Original line number Diff line number Diff line
@@ -135,6 +135,12 @@ static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) 
{

	uint32_t tmp;



	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	/* Setup L2 cache */

	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -190,6 +196,12 @@ static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) 


static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)

{

	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

		     0xFFFFFFFF);

	WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
@@ -326,6 +338,13 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, 
					  bool value)

{

	u32 tmp;



	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);

	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,

			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

+19 −0
Original line number Diff line number Diff line
@@ -134,6 +134,12 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 
{

	uint32_t tmp;



	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	/* Setup L2 cache */

	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -189,6 +195,12 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) 


static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)

{

	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	WREG32_SOC15(MMHUB, 0,

		     mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,

		     0xFFFFFFFF);
@@ -318,6 +330,13 @@ void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) 
void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)

{

	u32 tmp;



	/* These registers are not accessible to VF-SRIOV.

	 * The PF will program them instead.

	 */

	if (amdgpu_sriov_vf(adev))

		return;



	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);

	tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,

			    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+1 −0
Original line number Diff line number Diff line
@@ -2196,6 +2196,7 @@ void amdgpu_dm_update_connector_after_detect( 


			drm_connector_update_edid_property(connector,

							   aconnector->edid);

			drm_add_edid_modes(connector, aconnector->edid);



			if (aconnector->dc_link->aux_mode)

				drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,