Commit b8d85bb5 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'drm-msm-next-2023-04-10' of https://gitlab.freedesktop.org/drm/msm into drm-next 

main pull request for v6.4

Core Display:
============
* Bugfixes for error handling during probe
* rework UBWC decoder programming
* prepare_commit cleanup
* bindings for SM8550 (MDSS, DPU), SM8450 (DP)
* timeout calculation fixup
* atomic: use drm_crtc_next_vblank_start() instead of our own
  custom thing to calculate the start of next vblank

DP:
==
* interrupts cleanup

DPU:
===
* DSPP sub-block flush on sc7280
* support AR30 in addition to XR30 format
* Allow using REC_0 and REC_1 to handle wide (4k) RGB planes
* Split the HW catalog into individual per-SoC files

DSI:
===
* rework DSI instance ID detection on obscure platforms

GPU:
===
* uapi C++ compatibility fix
* a6xx: More robust gdsc reset
* a3xx and a4xx devfreq support
* update generated headers
* various cleanups and fixes
* GPU and GEM updates to avoid allocations which could trigger
  reclaim (shrinker) in fence signaling path
* dma-fence deadline hint support and wait-boost
* a640 speedbin support
* a650 speedbin support

Conflicts in drivers/gpu/drm/msm/adreno/adreno_gpu.c:

Conflict between the 7fa5047a ("drm: Use of_property_present() for
testing DT property presence") and 9f251f93 ("drm/msm/adreno: Use
OPP for every GPU generation"). The latter removed the of_ function
call outright, so I went with what's in the PR unchanged.

From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvwuj5tabyW910+N-B=5kFNAC7QNYoQ=0xi3roBjQvFFQ@mail.gmail.com


Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
parents 838ac90d ac7e7c9c

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

+15 −10
Original line number Diff line number Diff line
@@ -15,7 +15,8 @@ description: | 


properties:

  compatible:

    enum:

    oneOf:

      - enum:

          - qcom,sc7180-dp

          - qcom,sc7280-dp

          - qcom,sc7280-edp
@@ -25,6 +26,10 @@ properties: 
          - qcom,sc8280xp-edp

          - qcom,sdm845-dp

          - qcom,sm8350-dp

      - items:

          - enum:

              - qcom,sm8450-dp

          - const: qcom,sm8350-dp



  reg:

    minItems: 4

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

+5 −4
Original line number Diff line number Diff line
@@ -25,16 +25,16 @@ properties: 
              - qcom,sc7280-dsi-ctrl

              - qcom,sdm660-dsi-ctrl

              - qcom,sdm845-dsi-ctrl

              - qcom,sm6115-dsi-ctrl

              - qcom,sm8150-dsi-ctrl

              - qcom,sm8250-dsi-ctrl

              - qcom,sm8350-dsi-ctrl

              - qcom,sm8450-dsi-ctrl

              - qcom,sm8550-dsi-ctrl

          - const: qcom,mdss-dsi-ctrl

      - items:

      - enum:

              - dsi-ctrl-6g-qcm2290

          - const: qcom,mdss-dsi-ctrl

          - qcom,dsi-ctrl-6g-qcm2290

          - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible

        deprecated: true



  reg:
@@ -351,6 +351,7 @@ allOf: 
          contains:

            enum:

              - qcom,sdm845-dsi-ctrl

              - qcom,sm6115-dsi-ctrl

    then:

      properties:

        clocks:

Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml

+8 −2
Original line number Diff line number Diff line
@@ -40,6 +40,12 @@ patternProperties: 
    type: object

    properties:

      compatible:

        oneOf:

          - items:

              - const: qcom,sm6115-dsi-ctrl

              - const: qcom,mdss-dsi-ctrl

          - description: Old binding, please don't use

            deprecated: true

            const: qcom,dsi-ctrl-6g-qcm2290



  "^phy@[0-9a-f]+$":
@@ -114,7 +120,7 @@ examples: 
        };



        dsi@5e94000 {

            compatible = "qcom,dsi-ctrl-6g-qcm2290";

            compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";

            reg = <0x05e94000 0x400>;

            reg-names = "dsi_ctrl";

Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml

+3 −3
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ patternProperties: 
    type: object

    properties:

      compatible:

        const: qcom,dsi-phy-5nm-8450

        const: qcom,sm8450-dsi-phy-5nm



required:

  - compatible
@@ -254,7 +254,7 @@ examples: 
        };



        dsi0_phy: phy@ae94400 {

            compatible = "qcom,dsi-phy-5nm-8450";

            compatible = "qcom,sm8450-dsi-phy-5nm";

            reg = <0x0ae94400 0x200>,

                  <0x0ae94600 0x280>,

                  <0x0ae94900 0x260>;
@@ -325,7 +325,7 @@ examples: 
        };



        dsi1_phy: phy@ae96400 {

            compatible = "qcom,dsi-phy-5nm-8450";

            compatible = "qcom,sm8450-dsi-phy-5nm";

            reg = <0x0ae96400 0x200>,

                  <0x0ae96600 0x280>,

                  <0x0ae96900 0x260>;

Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml

0 → 100644
+133 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SM8550 Display DPU



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>



$ref: /schemas/display/msm/dpu-common.yaml#



properties:

  compatible:

    const: qcom,sm8550-dpu



  reg:

    items:

      - description: Address offset and size for mdp register set

      - description: Address offset and size for vbif register set



  reg-names:

    items:

      - const: mdp

      - const: vbif



  clocks:

    items:

      - description: Display AHB

      - description: Display hf axi

      - description: Display MDSS ahb

      - description: Display lut

      - description: Display core

      - description: Display vsync



  clock-names:

    items:

      - const: bus

      - const: nrt_bus

      - const: iface

      - const: lut

      - const: core

      - const: vsync



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8550-dispcc.h>

    #include <dt-bindings/clock/qcom,sm8550-gcc.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-controller@ae01000 {

        compatible = "qcom,sm8550-dpu";

        reg = <0x0ae01000 0x8f000>,

              <0x0aeb0000 0x2008>;

        reg-names = "mdp", "vbif";



        clocks = <&gcc GCC_DISP_AHB_CLK>,

                <&gcc GCC_DISP_HF_AXI_CLK>,

                <&dispcc DISP_CC_MDSS_AHB_CLK>,

                <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,

                <&dispcc DISP_CC_MDSS_MDP_CLK>,

                <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

        clock-names = "bus",

                      "nrt_bus",

                      "iface",

                      "lut",

                      "core",

                      "vsync";



        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;

        assigned-clock-rates = <19200000>;



        operating-points-v2 = <&mdp_opp_table>;

        power-domains = <&rpmhpd SM8550_MMCX>;



        interrupt-parent = <&mdss>;

        interrupts = <0>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                dpu_intf1_out: endpoint {

                    remote-endpoint = <&dsi0_in>;

                };

            };



            port@1 {

                reg = <1>;

                dpu_intf2_out: endpoint {

                    remote-endpoint = <&dsi1_in>;

                };

            };

        };



        mdp_opp_table: opp-table {

            compatible = "operating-points-v2";



            opp-200000000 {

                opp-hz = /bits/ 64 <200000000>;

                required-opps = <&rpmhpd_opp_low_svs>;

            };



            opp-325000000 {

                opp-hz = /bits/ 64 <325000000>;

                required-opps = <&rpmhpd_opp_svs>;

            };



            opp-375000000 {

                opp-hz = /bits/ 64 <375000000>;

                required-opps = <&rpmhpd_opp_svs_l1>;

            };



            opp-514000000 {

                opp-hz = /bits/ 64 <514000000>;

                required-opps = <&rpmhpd_opp_nom>;

            };

        };

    };

...