Commit b852ee68 authored by Jason-JH.Lin's avatar Jason-JH.Lin Committed by Matthias Brugger
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arm64: dts: mt8195: Add display node for vdosys0 



Add display node for vdosys0 of mt8195.

Signed-off-by: default avatarJason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: default avatarTinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220811025813.21492-21-tinghan.shen@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 329239a1

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+93 −0
Original line number Diff line number Diff line
@@ -1958,6 +1958,7 @@ 
		vdosys0: syscon@1c01a000 {

			compatible = "mediatek,mt8195-mmsys", "syscon";

			reg = <0 0x1c01a000 0 0x1000>;

			mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;

			#clock-cells = <1>;

		};
@@ -1973,6 +1974,98 @@ 
			power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;

		};



		ovl0: ovl@1c000000 {

			compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";

			reg = <0 0x1c000000 0 0x1000>;

			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;

			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;

		};



		rdma0: rdma@1c002000 {

			compatible = "mediatek,mt8195-disp-rdma";

			reg = <0 0x1c002000 0 0x1000>;

			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;

			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;

		};



		color0: color@1c003000 {

			compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";

			reg = <0 0x1c003000 0 0x1000>;

			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;

		};



		ccorr0: ccorr@1c004000 {

			compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";

			reg = <0 0x1c004000 0 0x1000>;

			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;

		};



		aal0: aal@1c005000 {

			compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";

			reg = <0 0x1c005000 0 0x1000>;

			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;

		};



		gamma0: gamma@1c006000 {

			compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";

			reg = <0 0x1c006000 0 0x1000>;

			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;

		};



		dither0: dither@1c007000 {

			compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";

			reg = <0 0x1c007000 0 0x1000>;

			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;

		};



		dsc0: dsc@1c009000 {

			compatible = "mediatek,mt8195-disp-dsc";

			reg = <0 0x1c009000 0 0x1000>;

			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;

		};



		merge0: merge@1c014000 {

			compatible = "mediatek,mt8195-disp-merge";

			reg = <0 0x1c014000 0 0x1000>;

			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;

			mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;

		};



		mutex: mutex@1c016000 {

			compatible = "mediatek,mt8195-disp-mutex";

			reg = <0 0x1c016000 0 0x1000>;

			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;

			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;

			mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;

		};



		larb0: larb@1c018000 {

			compatible = "mediatek,mt8195-smi-larb";

			reg = <0 0x1c018000 0 0x1000>;