Commit 329239a1 authored by Jason-JH.Lin's avatar Jason-JH.Lin Committed by Matthias Brugger
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arm64: dts: mt8195: Add gce node 



Add gce node and gce alias to mt8195 device tree.

Signed-off-by: default avatarJason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: default avatarTinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220811025813.21492-20-tinghan.shen@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 3b5838d1

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 


/dts-v1/;

#include <dt-bindings/clock/mt8195-clk.h>

#include <dt-bindings/gce/mt8195-gce.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/memory/mt8195-memory-port.h>
@@ -19,6 +20,11 @@ 
	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		gce0 = &gce0;

		gce1 = &gce1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -736,6 +742,22 @@ 
			#iommu-cells = <1>;

		};



		gce0: mailbox@10320000 {

			compatible = "mediatek,mt8195-gce";

			reg = <0 0x10320000 0 0x4000>;

			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;

			#mbox-cells = <2>;

			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;

		};



		gce1: mailbox@10330000 {

			compatible = "mediatek,mt8195-gce";

			reg = <0 0x10330000 0 0x4000>;

			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;

			#mbox-cells = <2>;

			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;

		};



		scp: scp@10500000 {

			compatible = "mediatek,mt8195-scp";

			reg = <0 0x10500000 0 0x100000>,