Unverified Commit b7485ec8 authored by Ajit Kumar Pandey's avatar Ajit Kumar Pandey Committed by Mark Brown
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ASoC: SOF: amd: Flush cache after ATU_BASE_ADDR_GRP register update 



ACP_SRAM_PTE block has cache that needs to be flushed after every
PTE updates. This patch updates ACPAXI2AXI_ATU_CTRL register to
flush cache after updating PTE with stream physical address.

Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: default avatarAjit Kumar Pandey <AjitKumar.Pandey@amd.com>
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20220304205733.62233-5-pierre-louis.bossart@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 9c2611b2

sound/soc/sof/amd/acp-stream.c

+3 −0
Original line number Diff line number Diff line
@@ -115,6 +115,9 @@ int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *strea 
		offset += 8;

	}



	/* Flush ATU Cache after PTE Update */

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);



	return 0;

}