Commit b70df82b authored by Andi Shyti's avatar Andi Shyti
Browse files

drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control and in the CS 



Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).

For the copy engine add MI_FLUSH_DW_CCS (bit 16) in the command
streamer.

Fixes: 972282c4 ("drm/i915/gen12: Add aux table invalidate for all engines")
Requires: 8da173db894a ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet")
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: <stable@vger.kernel.org> # v5.8+
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: default avatarNirmoy Das <nirmoy.das@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-6-andi.shyti@linux.intel.com
parent f2dcd21d

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+11 −0
Original line number Diff line number Diff line
@@ -230,6 +230,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) 


		bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;



		/*

		 * When required, in MTL and beyond platforms we

		 * need to set the CCS_FLUSH bit in the pipe control

		 */

		if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))

			bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;



		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;

		bit_group_1 |= PIPE_CONTROL_FLUSH_L3;

		bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -356,6 +363,10 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) 
		cmd |= MI_INVALIDATE_TLB;

		if (rq->engine->class == VIDEO_DECODE_CLASS)

			cmd |= MI_INVALIDATE_BSD;



		if (gen12_needs_ccs_aux_inv(rq->engine) &&

		    rq->engine->class == COPY_ENGINE_CLASS)

			cmd |= MI_FLUSH_DW_CCS;

	}



	*cs++ = cmd;

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

+1 −0
Original line number Diff line number Diff line
@@ -299,6 +299,7 @@ 
#define   PIPE_CONTROL_QW_WRITE				(1<<14)

#define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)

#define   PIPE_CONTROL_DEPTH_STALL			(1<<13)

#define   PIPE_CONTROL_CCS_FLUSH			(1<<13) /* MTL+ */

#define   PIPE_CONTROL_WRITE_FLUSH			(1<<12)

#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */

#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on ILK */