Commit b64baafa authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-loongson' and 'clk-qcom' into clk-next 

* clk-loongson:
  dt-bindings: clock: add loongson-2 clock
  dt-bindings: clock: add loongson-2 clock include file

* clk-qcom: (143 commits)
  clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP
  clk: qcom: Revert sync_state based clk_disable_unused
  dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml
  clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC
  clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC
  dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property
  clk: qcom: cpu-8996: add missing cputype include
  clk: qcom: gcc-sa8775p: remove unused variables
  clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platform
  clk: qcom: add msm8996 Core Bus Framework (CBF) support
  dt-bindings: clock: qcom,msm8996-cbf: Describe the MSM8996 CBF clock controller
  clk: qcom: add the driver for the MSM8996 APCS clocks
  clk: qcom: gcc-qcs404: fix duplicate initializer warning
  clk: qcom: cpu-8996: change setup sequence to follow vendor kernel
  clk: qcom: cpu-8996: fix PLL clock ops
  clk: qcom: cpu-8996: fix ACD initialization
  clk: qcom: cpu-8996: fix PLL configuration sequence
  clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init call
  clk: qcom: cpu-8996: setup PLLs before registering clocks
  clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cb
  ...
parents 60950df7 8ffba409 90039f37

Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml

0 → 100644
+63 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Loongson-2 SoC Clock Control Module



maintainers:

  - Yinbo Zhu <zhuyinbo@loongson.cn>



description: |

  Loongson-2 SoC clock control module is an integrated clock controller, which

  generates and supplies to all modules.



properties:

  compatible:

    enum:

      - loongson,ls2k-clk



  reg:

    maxItems: 1



  clocks:

    items:

      - description: 100m ref



  clock-names:

    items:

      - const: ref_100m



  '#clock-cells':

    const: 1

    description:

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h

      for the full list of Loongson-2 SoC clock IDs.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    ref_100m: clock-ref-100m {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <100000000>;

        clock-output-names = "ref_100m";

    };



    clk: clock-controller@1fe00480 {

        compatible = "loongson,ls2k-clk";

        reg = <0x1fe00480 0x58>;

        #clock-cells = <1>;

        clocks = <&ref_100m>;

        clock-names = "ref_100m";

    };

Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml

+18 −2
Original line number Diff line number Diff line
@@ -21,12 +21,16 @@ properties: 


  clocks:

    items:

      - description: AHB

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source



  clock-names:

    items:

      - const: iface

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk



  '#clock-cells':
@@ -38,9 +42,18 @@ properties: 
  '#power-domain-cells':

    const: 1



  power-domains:

    items:

      - description: MMCX power domain



  reg:

    maxItems: 1



  required-opps:

    maxItems: 1

    description:

      OPP node describing required MMCX performance point.



required:

  - compatible

  - reg
@@ -54,13 +67,16 @@ additionalProperties: false 


examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sm8250.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@ad00000 {

      compatible = "qcom,sm8250-camcc";

      reg = <0x0ad00000 0x10000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

      clocks = <&gcc GCC_CAMERA_AHB_CLK>,

               <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>;

      clock-names = "bi_tcxo", "sleep_clk";

      clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml

+44 −0
Original line number Diff line number Diff line
@@ -25,6 +25,30 @@ properties: 
  compatible:

    const: qcom,gcc-apq8084



  clocks:

    items:

      - description: XO source

      - description: Sleep clock source

      - description: UFS RX symbol 0 clock

      - description: UFS RX symbol 1 clock

      - description: UFS TX symbol 0 clock

      - description: UFS TX symbol 1 clock

      - description: SATA ASIC0 clock

      - description: SATA RX clock

      - description: PCIe PIPE clock



  clock-names:

    items:

      - const: xo

      - const: sleep_clk

      - const: ufs_rx_symbol_0_clk_src

      - const: ufs_rx_symbol_1_clk_src

      - const: ufs_tx_symbol_0_clk_src

      - const: ufs_tx_symbol_1_clk_src

      - const: sata_asic0_clk

      - const: sata_rx_clk

      - const: pcie_pipe



required:

  - compatible
@@ -32,11 +56,31 @@ unevaluatedProperties: false 


examples:

  - |

    /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */

    clock-controller@fc400000 {

        compatible = "qcom,gcc-apq8084";

        reg = <0xfc400000 0x4000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        #power-domain-cells = <1>;



        clocks = <&xo_board>,

                 <&sleep_clk>,

                 <&ufsphy 0>,

                 <&ufsphy 1>,

                 <&ufsphy 2>,

                 <&ufsphy 3>,

                 <&sata 0>,

                 <&sata 1>,

                 <&pcie_phy>;

        clock-names = "xo",

                      "sleep_clk",

                      "ufs_rx_symbol_0_clk_src",

                      "ufs_rx_symbol_1_clk_src",

                      "ufs_tx_symbol_0_clk_src",

                      "ufs_tx_symbol_1_clk_src",

                      "sata_asic0_clk",

                      "sata_rx_clk",

                      "pcie_pipe";

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml

+1 −5
Original line number Diff line number Diff line
@@ -25,7 +25,6 @@ properties: 
      - description: Board XO source

      - description: Sleep clock source

      - description: Audio reference clock (Optional clock)

      - description: PLL test clock source (Optional clock)

    minItems: 2



  clock-names:
@@ -33,7 +32,6 @@ properties: 
      - const: xo

      - const: sleep_clk

      - const: aud_ref_clk # Optional clock

      - const: core_bi_pll_test_se # Optional clock

    minItems: 2



required:
@@ -57,11 +55,9 @@ examples: 
      reg = <0x00100000 0xb0000>;

      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,

               <&sleep>,

               <0>,

               <0>;

      clock-names = "xo",

                    "sleep_clk",

                    "aud_ref_clk",

                    "core_bi_pll_test_se";

                    "aud_ref_clk";

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml

+22 −16
Original line number Diff line number Diff line
@@ -20,26 +20,31 @@ properties: 
  compatible:

    const: qcom,gcc-qcs404



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  reg:

    maxItems: 1



  protected-clocks:

    description:

      Protected clock specifier list as per common clock binding.

  clocks:

    items:

      - description: XO source

      - description: Sleep clock source

      - description: PCIe 0 PIPE clock (optional)

      - description: DSI phy instance 0 dsi clock

      - description: DSI phy instance 0 byte clock

      - description: HDMI phy PLL clock



  clock-names:

    items:

      - const: cxo

      - const: sleep_clk

      - const: pcie_0_pipe_clk_src

      - const: dsi0pll

      - const: dsi0pllbyte

      - const: hdmi_pll



required:

  - compatible

  - reg

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false

allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |
@@ -48,5 +53,6 @@ examples: 
      reg = <0x01800000 0x80000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...