Commit b3d971ec authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2022-02-18' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular fixes for rc5, nothing really stands out, mostly some amdgpu
  and i915 fixes with mediatek, radeon and some misc fixes.

  cma-helper:
   - set VM_DONTEXPAND

  atomic:
   - error handling fix

  mediatek:
   - fix probe defer loop with external bridge

  amdgpu:
   - Stable pstate clock fixes for Dimgrey Cavefish and Beige Goby
   - S0ix SDMA fix
   - Yellow Carp GPU reset fix

  radeon:
   - Backlight fix for iMac 12,1

  i915:
   - GVT kerneldoc cleanup.
   - GVT Kconfig should depend on X86
   - Prevent out of range access in SWSCI display code
   - Fix mbus join and dbuf slice config lookup
   - Fix inverted priority selection in the TTM backend
   - Fix FBC plane end Y offset check"

* tag 'drm-fixes-2022-02-18' of git://anongit.freedesktop.org/drm/drm:
  drm/atomic: Don't pollute crtc_state->mode_blob with error pointers
  drm/radeon: Fix backlight control on iMac 12,1
  drm/amd/pm: correct the sequence of sending gpu reset msg
  drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.
  drm/amd/pm: correct UMD pstate clocks for Dimgrey Cavefish and Beige Goby
  drm/i915/fbc: Fix the plane end Y offset check
  drm/i915/opregion: check port number bounds for SWSCI display power state
  drm/i915/ttm: tweak priority hint selection
  drm/i915: Fix mbus join config lookup
  drm/i915: Fix dbuf slice config lookup
  drm/cma-helper: Set VM_DONTEXPAND for mmap
  drm/mediatek: mtk_dsi: Avoid EPROBE_DEFER loop with external bridge
  drm/i915/gvt: Make DRM_I915_GVT depend on X86
  drm/i915/gvt: clean up kernel-doc in gtt.c
parents 8b97cae3 5666b610

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+8 −0
Original line number Diff line number Diff line
@@ -2057,6 +2057,10 @@ static int sdma_v4_0_suspend(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	/* SMU saves SDMA state for us */

	if (adev->in_s0ix)

		return 0;



	return sdma_v4_0_hw_fini(adev);

}
@@ -2064,6 +2068,10 @@ static int sdma_v4_0_resume(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	/* SMU restores SDMA state for us */

	if (adev->in_s0ix)

		return 0;



	return sdma_v4_0_hw_init(adev);

}

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+21 −5
Original line number Diff line number Diff line
@@ -1238,21 +1238,37 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 
				&dpm_context->dpm_tables.soc_table;

	struct smu_umd_pstate_table *pstate_table =

				&smu->pstate_table;

	struct amdgpu_device *adev = smu->adev;



	pstate_table->gfxclk_pstate.min = gfx_table->min;

	pstate_table->gfxclk_pstate.peak = gfx_table->max;

	if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)

		pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;



	pstate_table->uclk_pstate.min = mem_table->min;

	pstate_table->uclk_pstate.peak = mem_table->max;

	if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)

		pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;



	pstate_table->socclk_pstate.min = soc_table->min;

	pstate_table->socclk_pstate.peak = soc_table->max;

	if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)



	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;

		break;

	case CHIP_DIMGREY_CAVEFISH:

		pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;

		break;

	case CHIP_BEIGE_GOBY:

		pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;

		break;

	default:

		break;

	}



	return 0;

}

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h

+8 −0
Original line number Diff line number Diff line
@@ -33,6 +33,14 @@ typedef enum { 
#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK    960

#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK    1000



#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK 1950

#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK 960

#define DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK 676



#define BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK 2200

#define BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK 960

#define BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK 1000



extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);



#endif

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

+2 −7
Original line number Diff line number Diff line
@@ -282,14 +282,9 @@ static int yellow_carp_post_smu_init(struct smu_context *smu) 


static int yellow_carp_mode_reset(struct smu_context *smu, int type)

{

	int ret = 0, index = 0;



	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,

				SMU_MSG_GfxDeviceDriverReset);

	if (index < 0)

		return index == -EACCES ? 0 : index;

	int ret = 0;



	ret = smu_cmn_send_smc_msg_with_param(smu, (uint16_t)index, type, NULL);

	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);

	if (ret)

		dev_err(smu->adev->dev, "Failed to mode reset!\n");

drivers/gpu/drm/drm_atomic_uapi.c

+8 −6
Original line number Diff line number Diff line
@@ -76,15 +76,17 @@ int drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, 
	state->mode_blob = NULL;



	if (mode) {

		struct drm_property_blob *blob;



		drm_mode_convert_to_umode(&umode, mode);

		state->mode_blob =

			drm_property_create_blob(state->crtc->dev,

						 sizeof(umode),

						 &umode);

		if (IS_ERR(state->mode_blob))

			return PTR_ERR(state->mode_blob);

		blob = drm_property_create_blob(crtc->dev,

						sizeof(umode), &umode);

		if (IS_ERR(blob))

			return PTR_ERR(blob);



		drm_mode_copy(&state->mode, mode);



		state->mode_blob = blob;

		state->enable = true;

		drm_dbg_atomic(crtc->dev,

			       "Set [MODE:%s] for [CRTC:%d:%s] state %p\n",