Commit 5666b610 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2022-02-17' of... 

Merge tag 'drm-intel-fixes-2022-02-17' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- GVT kerneldoc cleanup. (Randy Dunlap)
- GVT Kconfig should depend on X86. (Siva Mullati)
- Prevent out of range access in SWSCI display code. (Jani Nikula)
- Fix mbus join and dbuf slice config lookup. (Ville Syrjälä)
- Fix inverted priority selection in the TTM backend. (Matthew Auld)
- Fix FBC plane end Y offset check. (Ville Syrjälä)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Yg4lA6k8+xp8u3aB@tursulin-mobl2
parents babb1fc3 26ace879

drivers/gpu/drm/i915/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ config DRM_I915_USERPTR 
config DRM_I915_GVT

	bool "Enable Intel GVT-g graphics virtualization host support"

	depends on DRM_I915

	depends on X86

	depends on 64BIT

	default n

	help

drivers/gpu/drm/i915/display/intel_fbc.c

+2 −1
Original line number Diff line number Diff line
@@ -1115,7 +1115,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, 


	/* Wa_22010751166: icl, ehl, tgl, dg1, rkl */

	if (DISPLAY_VER(i915) >= 11 &&

	    (plane_state->view.color_plane[0].y + drm_rect_height(&plane_state->uapi.src)) & 3) {

	    (plane_state->view.color_plane[0].y +

	     (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {

		plane_state->no_fbc_reason = "plane end Y offset misaligned";

		return false;

	}

drivers/gpu/drm/i915/display/intel_opregion.c

+15 −0
Original line number Diff line number Diff line
@@ -360,6 +360,21 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 
		port++;

	}



	/*

	 * The port numbering and mapping here is bizarre. The now-obsolete

	 * swsci spec supports ports numbered [0..4]. Port E is handled as a

	 * special case, but port F and beyond are not. The functionality is

	 * supposed to be obsolete for new platforms. Just bail out if the port

	 * number is out of bounds after mapping.

	 */

	if (port > 4) {

		drm_dbg_kms(&dev_priv->drm,

			    "[ENCODER:%d:%s] port %c (index %u) out of bounds for display power state notification\n",

			    intel_encoder->base.base.id, intel_encoder->base.name,

			    port_name(intel_encoder->port), port);

		return -EINVAL;

	}



	if (!enable)

		parm |= 4 << 8;

drivers/gpu/drm/i915/gem/i915_gem_ttm.c

+2 −4
Original line number Diff line number Diff line
@@ -842,11 +842,9 @@ void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj) 
	} else if (obj->mm.madv != I915_MADV_WILLNEED) {

		bo->priority = I915_TTM_PRIO_PURGE;

	} else if (!i915_gem_object_has_pages(obj)) {

		if (bo->priority < I915_TTM_PRIO_HAS_PAGES)

			bo->priority = I915_TTM_PRIO_HAS_PAGES;

	} else {

		if (bo->priority > I915_TTM_PRIO_NO_PAGES)

		bo->priority = I915_TTM_PRIO_NO_PAGES;

	} else {

		bo->priority = I915_TTM_PRIO_HAS_PAGES;

	}



	ttm_bo_move_to_lru_tail(bo, bo->resource, NULL);

drivers/gpu/drm/i915/gvt/gtt.c

+2 −2
Original line number Diff line number Diff line
@@ -1148,7 +1148,7 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se, 
	ops->set_pfn(se, s->shadow_page.mfn);

}



/**

/*

 * Check if can do 2M page

 * @vgpu: target vgpu

 * @entry: target pfn's gtt entry
@@ -2193,7 +2193,7 @@ static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, 
}



/**

 * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read

 * intel_vgpu_emulate_ggtt_mmio_read - emulate GTT MMIO register read

 * @vgpu: a vGPU

 * @off: register offset

 * @p_data: data will be returned to guest