Commit b311f5d3 authored by Imran Shaik's avatar Imran Shaik Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling 



Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.

Fixes: 1c9efb0b ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Signed-off-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Signed-off-by: default avatarImran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent df873243

drivers/clk/qcom/gcc-qdu1000.c

+6 −17
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/clk-provider.h>
@@ -370,16 +370,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { 
	{ .index = DT_TCXO_IDX },

};



static const struct parent_map gcc_parent_map_7[] = {

	{ P_PCIE_0_PIPE_CLK, 0 },

	{ P_BI_TCXO, 2 },

};



static const struct clk_parent_data gcc_parent_data_7[] = {

	{ .index = DT_PCIE_0_PIPE_CLK_IDX },

	{ .index = DT_TCXO_IDX },

};



static const struct parent_map gcc_parent_map_8[] = {

	{ P_BI_TCXO, 0 },

	{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -439,16 +429,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { 
	},

};



static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {

static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {

	.reg = 0x9d064,

	.shift = 0,

	.width = 2,

	.parent_map = gcc_parent_map_7,

	.clkr = {

		.hw.init = &(const struct clk_init_data) {

			.name = "gcc_pcie_0_pipe_clk_src",

			.parent_data = gcc_parent_data_7,

			.num_parents = ARRAY_SIZE(gcc_parent_data_7),

			.parent_data = &(const struct clk_parent_data){

				.index = DT_PCIE_0_PIPE_CLK_IDX,

			},

			.num_parents = 1,

			.ops = &clk_regmap_phy_mux_ops,

		},

	},