Commit df873243 authored by Imran Shaik's avatar Imran Shaik Committed by Bjorn Andersson
Browse files

dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs 



Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock
bindings for QDU1000 and QRU1000 SoCs. While at it, update the
maintainers list.

Signed-off-by: default avatarImran Shaik <quic_imrashai@quicinc.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent a27ac380

Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml

+2 −1
Original line number Diff line number Diff line
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000



maintainers:

  - Melody Olvera <quic_molvera@quicinc.com>

  - Taniya Das <quic_tdas@quicinc.com>

  - Imran Shaik <quic_imrashai@quicinc.com>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

include/dt-bindings/clock/qcom,qdu1000-gcc.h

+3 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */

/*

 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H
@@ -138,6 +138,8 @@ 
#define GCC_AGGRE_NOC_ECPRI_GSI_CLK			128

#define GCC_PCIE_0_PIPE_CLK_SRC				129

#define GCC_PCIE_0_PHY_AUX_CLK_SRC			130

#define GCC_GPLL1_OUT_EVEN				131

#define GCC_DDRSS_ECPRI_GSI_CLK				132



/* GCC resets */

#define GCC_ECPRI_CC_BCR				0