Commit b23ec74c authored Sep 30, 2022 by Catalin Marinas

Merge branches 'for-next/doc', 'for-next/sve', 'for-next/sysreg',...

Merge branches 'for-next/doc', 'for-next/sve', 'for-next/sysreg', 'for-next/gettimeofday', 'for-next/stacktrace', 'for-next/atomics', 'for-next/el1-exceptions', 'for-next/a510-erratum-2658417', 'for-next/defconfig', 'for-next/tpidr2_el0' and 'for-next/ftrace', remote-tracking branch 'arm64/for-next/perf' into for-next/core

* arm64/for-next/perf:
  arm64: asm/perf_regs.h: Avoid C++-style comment in UAPI header
  arm64/sve: Add Perf extensions documentation
  perf: arm64: Add SVE vector granule register to user regs
  MAINTAINERS: add maintainers for Alibaba' T-Head PMU driver
  drivers/perf: add DDR Sub-System Driveway PMU driver for Yitian 710 SoC
  docs: perf: Add description for Alibaba's T-Head PMU driver

* for-next/doc:
  : Documentation/arm64 updates
  arm64/sve: Document our actual ABI for clearing registers on syscall

* for-next/sve:
  : SVE updates
  arm64/sysreg: Add hwcap for SVE EBF16

* for-next/sysreg: (35 commits)
  : arm64 system registers generation (more conversions)
  arm64/sysreg: Fix a few missed conversions
  arm64/sysreg: Convert ID_AA64AFRn_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64DFR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64FDR0_EL1 to automatic generation
  arm64/sysreg: Use feature numbering for PMU and SPE revisions
  arm64/sysreg: Add _EL1 into ID_AA64DFR0_EL1 definition names
  arm64/sysreg: Align field names in ID_AA64DFR0_EL1 with architecture
  arm64/sysreg: Add defintion for ALLINT
  arm64/sysreg: Convert SCXTNUM_EL1 to automatic generation
  arm64/sysreg: Convert TIPDR_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64PFR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64PFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64MMFR2_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64MMFR0_EL1 to automatic generation
  arm64/sysreg: Convert HCRX_EL2 to automatic generation
  arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 SME enumeration
  arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 BTI enumeration
  arm64/sysreg: Standardise naming of ID_AA64PFR1_EL1 fractional version fields
  arm64/sysreg: Standardise naming for MTE feature enumeration
  ...

* for-next/gettimeofday:
  : Use self-synchronising counter access in gettimeofday() (if FEAT_ECV)
  arm64: vdso: use SYS_CNTVCTSS_EL0 for gettimeofday
  arm64: alternative: patch alternatives in the vDSO
  arm64: module: move find_section to header

* for-next/stacktrace:
  : arm64 stacktrace cleanups and improvements
  arm64: stacktrace: track hyp stacks in unwinder's address space
  arm64: stacktrace: track all stack boundaries explicitly
  arm64: stacktrace: remove stack type from fp translator
  arm64: stacktrace: rework stack boundary discovery
  arm64: stacktrace: add stackinfo_on_stack() helper
  arm64: stacktrace: move SDEI stack helpers to stacktrace code
  arm64: stacktrace: rename unwind_next_common() -> unwind_next_frame_record()
  arm64: stacktrace: simplify unwind_next_common()
  arm64: stacktrace: fix kerneldoc comments

* for-next/atomics:
  : arm64 atomics improvements
  arm64: atomic: always inline the assembly
  arm64: atomics: remove LL/SC trampolines

* for-next/el1-exceptions:
  : Improve the reporting of EL1 exceptions
  arm64: rework BTI exception handling
  arm64: rework FPAC exception handling
  arm64: consistently pass ESR_ELx to die()
  arm64: die(): pass 'err' as long
  arm64: report EL1 UNDEFs better

* for-next/a510-erratum-2658417:
  : Cortex-A510: 2658417: remove BF16 support due to incorrect result
  arm64: errata: remove BF16 HWCAP due to incorrect result on Cortex-A510
  arm64: cpufeature: Expose get_arm64_ftr_reg() outside cpufeature.c
  arm64: cpufeature: Force HWCAP to be based on the sysreg visible to user-space

* for-next/defconfig:
  : arm64 defconfig updates
  arm64: defconfig: Add Coresight as module
  arm64: Enable docker support in defconfig
  arm64: defconfig: Enable memory hotplug and hotremove config
  arm64: configs: Enable all PMUs provided by Arm

* for-next/tpidr2_el0:
  : arm64 ptrace() support for TPIDR2_EL0
  kselftest/arm64: Add coverage of TPIDR2_EL0 ptrace interface
  arm64/ptrace: Support access to TPIDR2_EL0
  arm64/ptrace: Document extension of NT_ARM_TLS to cover TPIDR2_EL0
  kselftest/arm64: Add test coverage for NT_ARM_TLS

* for-next/ftrace:
  : arm64 ftraces updates/fixes
  arm64: ftrace: fix module PLTs with mcount
  arm64: module: Remove unused plt_entry_is_initialized()
  arm64: module: Make plt_equals_entry() static

parents aa3e49b6 d09ee410 81ff692a db74cd63 9025cebf 4b5e694e 78f6f5c9 830a2a4d 1bdb0fbb d56f66d2 2ddadec2 8cfb0857

Documentation/arm64/elf_hwcaps.rst

+3 −0

Original line number	Diff line number	Diff line
		@@ -272,6 +272,9 @@ HWCAP2_WFXT
		HWCAP2_EBF16
		Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.

		HWCAP2_SVE_EBF16
		Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0010.

		4. Unused AT_HWCAP bits
		-----------------------

Documentation/arm64/silicon-errata.rst

+2 −0

Original line number	Diff line number	Diff line
		@@ -110,6 +110,8 @@ stable kernels.
		+----------------+-----------------+-----------------+-----------------------------+
		\| ARM \| Cortex-A510 \| #2441009 \| ARM64_ERRATUM_2441009 \|
		+----------------+-----------------+-----------------+-----------------------------+
		\| ARM \| Cortex-A510 \| #2658417 \| ARM64_ERRATUM_2658417 \|
		+----------------+-----------------+-----------------+-----------------------------+
		\| ARM \| Cortex-A710 \| #2119858 \| ARM64_ERRATUM_2119858 \|
		+----------------+-----------------+-----------------+-----------------------------+
		\| ARM \| Cortex-A710 \| #2054223 \| ARM64_ERRATUM_2054223 \|

Documentation/arm64/sme.rst

+3 −0

Original line number	Diff line number	Diff line
		@@ -331,6 +331,9 @@ The regset data starts with struct user_za_header, containing:
		been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread
		when the coredump was generated.

		* The NT_ARM_TLS note will be extended to two registers, the second register
		will contain TPIDR2_EL0 on systems that support SME and will be read as
		zero with writes ignored otherwise.

		9. System runtime configuration
		--------------------------------

Documentation/arm64/sve.rst

+1 −1

Original line number	Diff line number	Diff line
		@@ -111,7 +111,7 @@ the SVE instruction set architecture.

		* On syscall, V0..V31 are preserved (as without SVE). Thus, bits [127:0] of
		Z0..Z31 are preserved. All other bits of Z0..Z31, and all of P0..P15 and FFR
		become unspecified on return from a syscall.
		become zero on return from a syscall.

		* The SVE registers are not used to pass arguments to or receive results from
		any syscall.

arch/arm64/Kconfig

+13 −0

Original line number	Diff line number	Diff line
		@@ -733,6 +733,19 @@ config ARM64_ERRATUM_2077057

		If unsure, say Y.

		config ARM64_ERRATUM_2658417
		bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
		default y
		help
		This option adds the workaround for ARM Cortex-A510 erratum 2658417.
		Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
		BFMMLA or VMMLA instructions in rare circumstances when a pair of
		A510 CPUs are using shared neon hardware. As the sharing is not
		discoverable by the kernel, hide the BF16 HWCAP to indicate that
		user-space should not be using these instructions.

		If unsure, say Y.

		config ARM64_ERRATUM_2119858
		bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
		default y