Commit 1bdb0fbb authored by James Morse's avatar James Morse Committed by Catalin Marinas
Browse files

arm64: errata: remove BF16 HWCAP due to incorrect result on Cortex-A510 



Cortex-A510's erratum #2658417 causes two BF16 instructions to return the
wrong result in rare circumstances when a pair of A510 CPUs are using
shared neon hardware.

The two instructions affected are BFMMLA and VMMLA, support for these is
indicated by the BF16 HWCAP. Remove it on affected platforms.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220909165938.3931307-4-james.morse@arm.com


[catalin.marinas@arm.com: add revision to the Kconfig help; remove .type]
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 445c953e

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -110,6 +110,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2441009        | ARM64_ERRATUM_2441009       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2658417        | ARM64_ERRATUM_2658417       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

arch/arm64/Kconfig

+13 −0
Original line number Diff line number Diff line
@@ -733,6 +733,19 @@ config ARM64_ERRATUM_2077057 


	  If unsure, say Y.



config ARM64_ERRATUM_2658417

	bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 2658417.

	  Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for

	  BFMMLA or VMMLA instructions in rare circumstances when a pair of

	  A510 CPUs are using shared neon hardware. As the sharing is not

	  discoverable by the kernel, hide the BF16 HWCAP to indicate that

	  user-space should not be using these instructions.



	  If unsure, say Y.



config ARM64_ERRATUM_2119858

	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"

	default y

arch/arm64/kernel/cpu_errata.c

+26 −0
Original line number Diff line number Diff line
@@ -121,6 +121,22 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 
	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);

}



static DEFINE_RAW_SPINLOCK(reg_user_mask_modification);

static void __maybe_unused

cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities *__unused)

{

	struct arm64_ftr_reg *regp;



	regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1);

	if (!regp)

		return;



	raw_spin_lock(&reg_user_mask_modification);

	if (regp->user_mask & ID_AA64ISAR1_EL1_BF16_MASK)

		regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK;

	raw_spin_unlock(&reg_user_mask_modification);

}



#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)	\

	.matches = is_affected_midr_range,			\

	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
@@ -691,6 +707,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		CAP_MIDR_RANGE_LIST(broken_aarch32_aes),

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2658417

	{

		.desc = "ARM erratum 2658417",

		.capability = ARM64_WORKAROUND_2658417,

		/* Cortex-A510 r0p0 - r1p1 */

		ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),

		MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)),

		.cpu_enable = cpu_clear_bf16_from_user_emulation,

	},

#endif

	{

	}

arch/arm64/tools/cpucaps

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ WORKAROUND_2038923 
WORKAROUND_2064142

WORKAROUND_2077057

WORKAROUND_2457168

WORKAROUND_2658417

WORKAROUND_TRBE_OVERWRITE_FILL_MODE

WORKAROUND_TSB_FLUSH_FAILURE

WORKAROUND_TRBE_WRITE_OUT_OF_RANGE