Loading drivers/thunderbolt/switch.c +28 −0 Original line number Diff line number Diff line Loading @@ -1330,6 +1330,34 @@ static int tb_port_clx_enable(struct tb_port *port, enum tb_clx clx) return __tb_port_clx_set(port, clx, true); } /** * tb_port_is_clx_enabled() - Is given CL state enabled * @port: USB4 port to check * @clx_mask: Mask of CL states to check * * Returns true if any of the given CL states is enabled for @port. */ bool tb_port_is_clx_enabled(struct tb_port *port, unsigned int clx_mask) { u32 val, mask = 0; int ret; if (!tb_port_clx_supported(port, clx_mask)) return false; if (clx_mask & TB_CL1) mask |= LANE_ADP_CS_1_CL0S_ENABLE | LANE_ADP_CS_1_CL1_ENABLE; if (clx_mask & TB_CL2) mask |= LANE_ADP_CS_1_CL2_ENABLE; ret = tb_port_read(port, &val, TB_CFG_PORT, port->cap_phy + LANE_ADP_CS_1, 1); if (ret) return false; return !!(val & mask); } static int tb_port_start_lane_initialization(struct tb_port *port) { int ret; Loading drivers/thunderbolt/tb.h +1 −0 Original line number Diff line number Diff line Loading @@ -1035,6 +1035,7 @@ void tb_port_lane_bonding_disable(struct tb_port *port); int tb_port_wait_for_link_width(struct tb_port *port, int width, int timeout_msec); int tb_port_update_credits(struct tb_port *port); bool tb_port_is_clx_enabled(struct tb_port *port, enum tb_clx clx); int tb_switch_find_vse_cap(struct tb_switch *sw, enum tb_switch_vse_cap vsec); int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap); Loading drivers/thunderbolt/tb_regs.h +1 −0 Original line number Diff line number Diff line Loading @@ -334,6 +334,7 @@ struct tb_regs_port_header { #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3 #define LANE_ADP_CS_1_CL0S_ENABLE BIT(10) #define LANE_ADP_CS_1_CL1_ENABLE BIT(11) #define LANE_ADP_CS_1_CL2_ENABLE BIT(12) #define LANE_ADP_CS_1_LD BIT(14) #define LANE_ADP_CS_1_LB BIT(15) #define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16) Loading Loading
drivers/thunderbolt/switch.c +28 −0 Original line number Diff line number Diff line Loading @@ -1330,6 +1330,34 @@ static int tb_port_clx_enable(struct tb_port *port, enum tb_clx clx) return __tb_port_clx_set(port, clx, true); } /** * tb_port_is_clx_enabled() - Is given CL state enabled * @port: USB4 port to check * @clx_mask: Mask of CL states to check * * Returns true if any of the given CL states is enabled for @port. */ bool tb_port_is_clx_enabled(struct tb_port *port, unsigned int clx_mask) { u32 val, mask = 0; int ret; if (!tb_port_clx_supported(port, clx_mask)) return false; if (clx_mask & TB_CL1) mask |= LANE_ADP_CS_1_CL0S_ENABLE | LANE_ADP_CS_1_CL1_ENABLE; if (clx_mask & TB_CL2) mask |= LANE_ADP_CS_1_CL2_ENABLE; ret = tb_port_read(port, &val, TB_CFG_PORT, port->cap_phy + LANE_ADP_CS_1, 1); if (ret) return false; return !!(val & mask); } static int tb_port_start_lane_initialization(struct tb_port *port) { int ret; Loading
drivers/thunderbolt/tb.h +1 −0 Original line number Diff line number Diff line Loading @@ -1035,6 +1035,7 @@ void tb_port_lane_bonding_disable(struct tb_port *port); int tb_port_wait_for_link_width(struct tb_port *port, int width, int timeout_msec); int tb_port_update_credits(struct tb_port *port); bool tb_port_is_clx_enabled(struct tb_port *port, enum tb_clx clx); int tb_switch_find_vse_cap(struct tb_switch *sw, enum tb_switch_vse_cap vsec); int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap); Loading
drivers/thunderbolt/tb_regs.h +1 −0 Original line number Diff line number Diff line Loading @@ -334,6 +334,7 @@ struct tb_regs_port_header { #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3 #define LANE_ADP_CS_1_CL0S_ENABLE BIT(10) #define LANE_ADP_CS_1_CL1_ENABLE BIT(11) #define LANE_ADP_CS_1_CL2_ENABLE BIT(12) #define LANE_ADP_CS_1_LD BIT(14) #define LANE_ADP_CS_1_LB BIT(15) #define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16) Loading