Commit 3846d011 authored by Mika Westerberg's avatar Mika Westerberg
Browse files

thunderbolt: Pass CL state bitmask to tb_port_clx_supported() 



Instead of testing just a single CL state we can pass a bitmask of
states to check. This makes it simpler for callers of the function.

We also add a check for CL2 even though not fully supported by the
driver yet.

Suggested-by: default avatarLukas Wunner <lukas@wunner.de>
Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
parent 95f8f1cb

drivers/thunderbolt/switch.c

+6 −11
Original line number Diff line number Diff line
@@ -1259,9 +1259,9 @@ static int tb_port_pm_secondary_disable(struct tb_port *port) 
}



/* Called for USB4 or Titan Ridge routers only */

static bool tb_port_clx_supported(struct tb_port *port, enum tb_clx clx)

static bool tb_port_clx_supported(struct tb_port *port, unsigned int clx_mask)

{

	u32 mask, val;

	u32 val, mask = 0;

	bool ret;



	/* Don't enable CLx in case of two single-lane links */
@@ -1279,17 +1279,12 @@ static bool tb_port_clx_supported(struct tb_port *port, enum tb_clx clx) 
		return false;

	}



	switch (clx) {

	case TB_CL1:

	if (clx_mask & TB_CL1) {

		/* CL0s and CL1 are enabled and supported together */

		mask = LANE_ADP_CS_0_CL0S_SUPPORT | LANE_ADP_CS_0_CL1_SUPPORT;

		break;



	/* For now we support only CL0s and CL1. Not CL2 */

	case TB_CL2:

	default:

		return false;

		mask |= LANE_ADP_CS_0_CL0S_SUPPORT | LANE_ADP_CS_0_CL1_SUPPORT;

	}

	if (clx_mask & TB_CL2)

		mask |= LANE_ADP_CS_0_CL2_SUPPORT;



	ret = tb_port_read(port, &val, TB_CFG_PORT,

			   port->cap_phy + LANE_ADP_CS_0, 1);

drivers/thunderbolt/tb.h

+2 −2
Original line number Diff line number Diff line
@@ -113,8 +113,8 @@ struct tb_switch_tmu { 
enum tb_clx {

	TB_CLX_DISABLE,

	/* CL0s and CL1 are enabled and supported together */

	TB_CL1,

	TB_CL2,

	TB_CL1 = BIT(0),

	TB_CL2 = BIT(1),

};



/**

drivers/thunderbolt/tb_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -324,6 +324,7 @@ struct tb_regs_port_header { 
#define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL	0x2

#define LANE_ADP_CS_0_CL0S_SUPPORT		BIT(26)

#define LANE_ADP_CS_0_CL1_SUPPORT		BIT(27)

#define LANE_ADP_CS_0_CL2_SUPPORT		BIT(28)

#define LANE_ADP_CS_1				0x01

#define LANE_ADP_CS_1_TARGET_SPEED_MASK		GENMASK(3, 0)

#define LANE_ADP_CS_1_TARGET_SPEED_GEN3		0xc