Commit b117b396 authored by Darren Powell's avatar Darren Powell Committed by Alex Deucher
Browse files

amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID 



Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot.
Patch ignores a .force_clk_levels(SMU_DCEFCLK) call and issues an
info message.

Signed-off-by: default avatarDarren Powell <darren.powell@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 20a5f5a9

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+4 −1
Original line number Diff line number Diff line
@@ -1443,7 +1443,6 @@ static int navi10_force_clk_levels(struct smu_context *smu, 
	case SMU_SOCCLK:

	case SMU_MCLK:

	case SMU_UCLK:

	case SMU_DCEFCLK:

	case SMU_FCLK:

		/* There is only 2 levels for fine grained DPM */

		if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1463,6 +1462,10 @@ static int navi10_force_clk_levels(struct smu_context *smu, 
		if (ret)

			return size;

		break;

	case SMU_DCEFCLK:

		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");

		break;



	default:

		break;

	}

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+3 −1
Original line number Diff line number Diff line
@@ -1127,7 +1127,6 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 
	case SMU_SOCCLK:

	case SMU_MCLK:

	case SMU_UCLK:

	case SMU_DCEFCLK:

	case SMU_FCLK:

		/* There is only 2 levels for fine grained DPM */

		if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1147,6 +1146,9 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu, 
		if (ret)

			goto forec_level_out;

		break;

	case SMU_DCEFCLK:

		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");

		break;

	default:

		break;

	}