Commit b0dacee2 authored by Joerg Roedel's avatar Joerg Roedel
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Merge branches 'apple/dart', 'arm/mediatek', 'arm/msm', 'arm/smmu',... 

Merge branches 'apple/dart', 'arm/mediatek', 'arm/msm', 'arm/smmu', 'ppc/pamu', 'x86/vt-d', 'x86/amd' and 'vfio-notifier-fix' into next
parents ee535434 de78657e 8b9ad480 b11deb2f cae8d1f5 0d647b33 42bb5aa0 fa7e9ecc

.mailmap

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@@ -45,6 +45,7 @@ Andrey Konovalov <andreyknvl@gmail.com> <andreyknvl@google.com> 
Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>

Andrey Ryabinin <ryabinin.a.a@gmail.com> <aryabinin@virtuozzo.com>

Andrzej Hajda <andrzej.hajda@intel.com> <a.hajda@samsung.com>

André Almeida <andrealmeid@igalia.com> <andrealmeid@collabora.com>

Andy Adamson <andros@citi.umich.edu>

Antoine Tenart <atenart@kernel.org> <antoine.tenart@bootlin.com>

Antoine Tenart <atenart@kernel.org> <antoine.tenart@free-electrons.com>
@@ -204,6 +205,7 @@ Juha Yrjola <at solidboot.com> 
Juha Yrjola <juha.yrjola@nokia.com>

Juha Yrjola <juha.yrjola@solidboot.com>

Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>

Kalle Valo <kvalo@kernel.org> <kvalo@codeaurora.org>

Kalyan Thota <quic_kalyant@quicinc.com> <kalyan_t@codeaurora.org>

Kay Sievers <kay.sievers@vrfy.org>

Kees Cook <keescook@chromium.org> <kees.cook@canonical.com>
@@ -249,6 +251,7 @@ Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com> 
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>

Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>

Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>

Martyna Szapar-Mudlaw <martyna.szapar-mudlaw@linux.intel.com> <martyna.szapar-mudlaw@intel.com>

Mathieu Othacehe <m.othacehe@gmail.com>

Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>

Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>

Documentation/arm64/memory-tagging-extension.rst

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@@ -228,10 +228,10 @@ Core dump support 
-----------------



The allocation tags for user memory mapped with ``PROT_MTE`` are dumped

in the core file as additional ``PT_ARM_MEMTAG_MTE`` segments. The

in the core file as additional ``PT_AARCH64_MEMTAG_MTE`` segments. The

program header for such segment is defined as:



:``p_type``: ``PT_ARM_MEMTAG_MTE``

:``p_type``: ``PT_AARCH64_MEMTAG_MTE``

:``p_flags``: 0

:``p_offset``: segment file offset

:``p_vaddr``: segment virtual address, same as the corresponding

Documentation/arm64/silicon-errata.rst

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@@ -189,6 +189,9 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Silver  | N/A             | ARM64_ERRATUM_1024718       |

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1286807       |

+----------------+-----------------+-----------------+-----------------------------+



+----------------+-----------------+-----------------+-----------------------------+

| Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |

+----------------+-----------------+-----------------+-----------------------------+

Documentation/devicetree/bindings/clock/imx8m-clock.yaml

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@@ -55,8 +55,6 @@ allOf: 
    then:

      properties:

        clocks:

          minItems: 7

          maxItems: 7

          items:

            - description: 32k osc

            - description: 25m osc
@@ -66,8 +64,6 @@ allOf: 
            - description: ext3 clock input

            - description: ext4 clock input

        clock-names:

          minItems: 7

          maxItems: 7

          items:

            - const: ckil

            - const: osc_25m

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

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@@ -22,7 +22,16 @@ properties: 
    const: microchip,mpfs-clkcfg



  reg:

    maxItems: 1

    items:

      - description: |

          clock config registers:

          These registers contain enable, reset & divider tables for the, cpu,

          axi, ahb and rtc/mtimer reference clocks as well as enable and reset

          for the peripheral clocks.

      - description: |

          mss pll dri registers:

          Block of registers responsible for dynamic reconfiguration of the mss

          pll



  clocks:

    maxItems: 1
@@ -51,7 +60,7 @@ examples: 
            #size-cells = <2>;

            clkcfg: clock-controller@20002000 {

                compatible = "microchip,mpfs-clkcfg";

                reg = <0x0 0x20002000 0x0 0x1000>;

                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;

                clocks = <&ref>;

                #clock-cells = <1>;

        };