Commit 0d647b33 authored by Lu Baolu's avatar Lu Baolu Committed by Joerg Roedel
Browse files

iommu/vt-d: Remove hard coding PGSNP bit in PASID entries 



As enforce_cache_coherency has been introduced into the iommu_domain_ops,
the kernel component which owns the iommu domain is able to opt-in its
requirement for force snooping support. The iommu driver has no need to
hard code the page snoop control bit in the PASID table entries anymore.

Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20220508123525.1973626-1-baolu.lu@linux.intel.com
Link: https://lore.kernel.org/r/20220510023407.2759143-9-baolu.lu@linux.intel.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent e8055226

drivers/iommu/intel/pasid.c

+0 −3
Original line number Diff line number Diff line
@@ -710,9 +710,6 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, 
	pasid_set_fault_enable(pte);

	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));



	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)

		pasid_set_pgsnp(pte);



	/*

	 * Since it is a second level only translation setup, we should

	 * set SRE bit as well (addresses are expected to be GPAs).