Commit b0d14d2a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-03-10' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Weekly fixes.

  msm and amdgpu are the vast majority of these, otherwise some
  straggler misc from last week for nouveau and cirrus and a mailmap
  update for a drm developer.

  mailmap:
   - add an entry

  nouveau:
   - fix system shutdown regression
   - build warning fix

  cirrus:
   - NULL ptr deref fix

  msm:
   - fix invalid ptr free in syncobj cleanup
   - sync GMU removal in teardown
   - a5xx preemption fixes
   - fix runpm imbalance
   - DPU hw fixes
   - stack corruption fix
   - clear DSPP reservation

  amdgpu:
   - Misc display fixes
   - UMC 8.10 fixes
   - Driver unload fixes
   - NBIO 7.3.0 fix
   - Error checking fixes for soc15, nv, soc21 read register interface
   - Fix video cap query for VCN 4.0.4

  amdkfd:
   - Fix return check in doorbell handling"

* tag 'drm-fixes-2023-03-10' of git://anongit.freedesktop.org/drm/drm: (42 commits)
  drm/amdgpu/soc21: Add video cap query support for VCN_4_0_4
  drm/amdgpu: fix error checking in amdgpu_read_mm_registers for nv
  drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc21
  drm/amdgpu: fix error checking in amdgpu_read_mm_registers for soc15
  drm/amdgpu: Fix the warning info when removing amdgpu device
  drm/amdgpu: fix return value check in kfd
  drm/amd: Fix initialization mistake for NBIO 7.3.0
  drm/amdgpu: Fix call trace warning and hang when removing amdgpu device
  mailmap: add mailmap entries for Faith.
  drm/msm: DEVFREQ_GOV_SIMPLE_ONDEMAND is no longer needed
  drm/amd/display: Update clock table to include highest clock setting
  drm/amd/pm: Enable ecc_info table support for smu v13_0_10
  drm/amdgpu: Support umc node harvest config on umc v8_10
  drm/connector: print max_requested_bpc in state debugfs
  drm/display: Don't block HDR_OUTPUT_METADATA on unknown EOTF
  drm/msm/dpu: clear DSPP reservations in rm release
  drm/msm/disp/dpu: fix sc7280_pp base offset
  drm/msm/dpu: fix stack smashing in dpu_hw_ctl_setup_blendstage
  drm/msm/dpu: don't use DPU_CLK_CTRL_CURSORn for DMA SSPP clocks
  drm/msm/dpu: fix clocks settings for msm8998 SSPP blocks
  ...
parents 388a8101 519b2331

.mailmap

+3 −0
Original line number Diff line number Diff line
@@ -136,6 +136,9 @@ Erik Kaneda <erik.kaneda@intel.com> <erik.schmauss@intel.com> 
Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>

Evgeniy Polyakov <johnpol@2ka.mipt.ru>

Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> <ezequiel@collabora.com>

Faith Ekstrand <faith.ekstrand@collabora.com> <jason@jlekstrand.net>

Faith Ekstrand <faith.ekstrand@collabora.com> <jason.ekstrand@intel.com>

Faith Ekstrand <faith.ekstrand@collabora.com> <jason.ekstrand@collabora.com>

Felipe W Damasio <felipewd@terra.com.br>

Felix Kuhling <fxkuehl@gmx.de>

Felix Moeller <felix@derklecks.de>

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+9 −1
Original line number Diff line number Diff line
@@ -543,6 +543,7 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 
	struct harvest_table *harvest_info;

	u16 offset;

	int i;

	uint32_t umc_harvest_config = 0;



	bhdr = (struct binary_header *)adev->mman.discovery_bin;

	offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
@@ -570,12 +571,17 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 
			adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;

			break;

		case UMC_HWID:

			umc_harvest_config |=

				1 << (le16_to_cpu(harvest_info->list[i].number_instance));

			(*umc_harvest_count)++;

			break;

		default:

			break;

		}

	}



	adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &

				~umc_harvest_config;

}



/* ================================================== */
@@ -1156,8 +1162,10 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 
						AMDGPU_MAX_SDMA_INSTANCES);

			}



			if (le16_to_cpu(ip->hw_id) == UMC_HWID)

			if (le16_to_cpu(ip->hw_id) == UMC_HWID) {

				adev->gmc.num_umc++;

				adev->umc.node_inst_num++;

			}



			for (k = 0; k < num_base_address; k++) {

				/*

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+1 −1
Original line number Diff line number Diff line
@@ -1315,7 +1315,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 


	if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||

	    !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||

	    adev->in_suspend || adev->shutdown)

	    adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))

		return;



	if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+1 −16
Original line number Diff line number Diff line
@@ -602,27 +602,14 @@ psp_cmd_submit_buf(struct psp_context *psp, 
		   struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)

{

	int ret;

	int index, idx;

	int index;

	int timeout = 20000;

	bool ras_intr = false;

	bool skip_unsupport = false;

	bool dev_entered;



	if (psp->adev->no_hw_access)

		return 0;



	dev_entered = drm_dev_enter(adev_to_drm(psp->adev), &idx);

	/*

	 * We allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring

	 * a lock in drm_dev_enter during driver unload because we must call

	 * drm_dev_unplug as the beginning  of unload driver sequence . It is very

	 * crucial that userspace can't access device instances anymore.

	 */

	if (!dev_entered)

		WARN_ON(psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_LOAD_ASD &&

			psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_UNLOAD_TA &&

			psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_INVOKE_CMD);



	memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);



	memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
@@ -686,8 +673,6 @@ psp_cmd_submit_buf(struct psp_context *psp, 
	}



exit:

	if (dev_entered)

		drm_dev_exit(idx);

	return ret;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h

+5 −2
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))



#define LOOP_UMC_NODE_INST(node_inst) \

		for ((node_inst) = 0; (node_inst) < adev->umc.node_inst_num; (node_inst)++)

		for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)



#define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \

		LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
@@ -69,7 +69,7 @@ struct amdgpu_umc { 
	/* number of umc instance with memory map register access */

	uint32_t umc_inst_num;



	/*number of umc node instance with memory map register access*/

	/* Total number of umc node instance including harvest one */

	uint32_t node_inst_num;



	/* UMC regiser per channel offset */
@@ -82,6 +82,9 @@ struct amdgpu_umc { 


	const struct amdgpu_umc_funcs *funcs;

	struct amdgpu_umc_ras *ras;



	/* active mask for umc node instance */

	unsigned long active_mask;

};



int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);