Commit 519b2331 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.3-2023-03-09' of...

Merge tag 'amd-drm-fixes-6.3-2023-03-09' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.3-2023-03-09:

amdgpu:
- Misc display fixes
- UMC 8.10 fixes
- Driver unload fixes
- NBIO 7.3.0 fix
- Error checking fixes for soc15, nv, soc21 read register interface
- Fix video cap query for VCN 4.0.4

amdkfd:
- Fix return check in doorbell handling

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230310031314.1296929-1-alexander.deucher@amd.com
parents 3a43e30b 6ce2ea07
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+9 −1
Original line number Diff line number Diff line
@@ -543,6 +543,7 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
	struct harvest_table *harvest_info;
	u16 offset;
	int i;
	uint32_t umc_harvest_config = 0;

	bhdr = (struct binary_header *)adev->mman.discovery_bin;
	offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
@@ -570,12 +571,17 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
			adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
			break;
		case UMC_HWID:
			umc_harvest_config |=
				1 << (le16_to_cpu(harvest_info->list[i].number_instance));
			(*umc_harvest_count)++;
			break;
		default:
			break;
		}
	}

	adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &
				~umc_harvest_config;
}

/* ================================================== */
@@ -1156,8 +1162,10 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
						AMDGPU_MAX_SDMA_INSTANCES);
			}

			if (le16_to_cpu(ip->hw_id) == UMC_HWID)
			if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
				adev->gmc.num_umc++;
				adev->umc.node_inst_num++;
			}

			for (k = 0; k < num_base_address; k++) {
				/*
+1 −1
Original line number Diff line number Diff line
@@ -1315,7 +1315,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)

	if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
	    !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
	    adev->in_suspend || adev->shutdown)
	    adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
		return;

	if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
+1 −16
Original line number Diff line number Diff line
@@ -602,27 +602,14 @@ psp_cmd_submit_buf(struct psp_context *psp,
		   struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
{
	int ret;
	int index, idx;
	int index;
	int timeout = 20000;
	bool ras_intr = false;
	bool skip_unsupport = false;
	bool dev_entered;

	if (psp->adev->no_hw_access)
		return 0;

	dev_entered = drm_dev_enter(adev_to_drm(psp->adev), &idx);
	/*
	 * We allow sending PSP messages LOAD_ASD and UNLOAD_TA without acquiring
	 * a lock in drm_dev_enter during driver unload because we must call
	 * drm_dev_unplug as the beginning  of unload driver sequence . It is very
	 * crucial that userspace can't access device instances anymore.
	 */
	if (!dev_entered)
		WARN_ON(psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_LOAD_ASD &&
			psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_UNLOAD_TA &&
			psp->cmd_buf_mem->cmd_id != GFX_CMD_ID_INVOKE_CMD);

	memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);

	memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
@@ -686,8 +673,6 @@ psp_cmd_submit_buf(struct psp_context *psp,
	}

exit:
	if (dev_entered)
		drm_dev_exit(idx);
	return ret;
}

+5 −2
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@
#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))

#define LOOP_UMC_NODE_INST(node_inst) \
		for ((node_inst) = 0; (node_inst) < adev->umc.node_inst_num; (node_inst)++)
		for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)

#define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
		LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
@@ -69,7 +69,7 @@ struct amdgpu_umc {
	/* number of umc instance with memory map register access */
	uint32_t umc_inst_num;

	/*number of umc node instance with memory map register access*/
	/* Total number of umc node instance including harvest one */
	uint32_t node_inst_num;

	/* UMC regiser per channel offset */
@@ -82,6 +82,9 @@ struct amdgpu_umc {

	const struct amdgpu_umc_funcs *funcs;
	struct amdgpu_umc_ras *ras;

	/* active mask for umc node instance */
	unsigned long active_mask;
};

int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
+0 −1
Original line number Diff line number Diff line
@@ -567,7 +567,6 @@ static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev)
	case IP_VERSION(8, 10, 0):
		adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM;
		adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM;
		adev->umc.node_inst_num = adev->gmc.num_umc;
		adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
		adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET;
		adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM;
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