Commit b0338e99 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/cpu' into perf/core 



Merge this branch because we changed the wrmsr*_safe() API and there's
a conflict.

Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 90574ebb 715c85b1

arch/x86/include/asm/msr.h

+3 −41
Original line number Diff line number Diff line
@@ -115,8 +115,8 @@ notrace static inline int native_write_msr_safe(unsigned int msr, 


extern unsigned long long native_read_tsc(void);



extern int native_rdmsr_safe_regs(u32 regs[8]);

extern int native_wrmsr_safe_regs(u32 regs[8]);

extern int rdmsr_safe_regs(u32 regs[8]);

extern int wrmsr_safe_regs(u32 regs[8]);



static __always_inline unsigned long long __native_read_tsc(void)

{
@@ -187,43 +187,6 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) 
	return err;

}



static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)

{

	u32 gprs[8] = { 0 };

	int err;



	gprs[1] = msr;

	gprs[7] = 0x9c5a203a;



	err = native_rdmsr_safe_regs(gprs);



	*p = gprs[0] | ((u64)gprs[2] << 32);



	return err;

}



static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)

{

	u32 gprs[8] = { 0 };



	gprs[0] = (u32)val;

	gprs[1] = msr;

	gprs[2] = val >> 32;

	gprs[7] = 0x9c5a203a;



	return native_wrmsr_safe_regs(gprs);

}



static inline int rdmsr_safe_regs(u32 regs[8])

{

	return native_rdmsr_safe_regs(regs);

}



static inline int wrmsr_safe_regs(u32 regs[8])

{

	return native_wrmsr_safe_regs(regs);

}



#define rdtscl(low)						\

	((low) = (u32)__native_read_tsc())
@@ -250,8 +213,7 @@ do { \ 


#endif	/* !CONFIG_PARAVIRT */





#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),		\

#define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val),		\

					     (u32)((val) >> 32))



#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))

arch/x86/include/asm/paravirt.h

+0 −39
Original line number Diff line number Diff line
@@ -128,21 +128,11 @@ static inline u64 paravirt_read_msr(unsigned msr, int *err) 
	return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);

}



static inline int paravirt_rdmsr_regs(u32 *regs)

{

	return PVOP_CALL1(int, pv_cpu_ops.rdmsr_regs, regs);

}



static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)

{

	return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);

}



static inline int paravirt_wrmsr_regs(u32 *regs)

{

	return PVOP_CALL1(int, pv_cpu_ops.wrmsr_regs, regs);

}



/* These should all do BUG_ON(_err), but our headers are too tangled. */

#define rdmsr(msr, val1, val2)			\

do {						\
@@ -176,9 +166,6 @@ do { \ 
	_err;					\

})



#define rdmsr_safe_regs(regs)	paravirt_rdmsr_regs(regs)

#define wrmsr_safe_regs(regs)	paravirt_wrmsr_regs(regs)



static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)

{

	int err;
@@ -186,32 +173,6 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) 
	*p = paravirt_read_msr(msr, &err);

	return err;

}

static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)

{

	u32 gprs[8] = { 0 };

	int err;



	gprs[1] = msr;

	gprs[7] = 0x9c5a203a;



	err = paravirt_rdmsr_regs(gprs);



	*p = gprs[0] | ((u64)gprs[2] << 32);



	return err;

}



static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)

{

	u32 gprs[8] = { 0 };



	gprs[0] = (u32)val;

	gprs[1] = msr;

	gprs[2] = val >> 32;

	gprs[7] = 0x9c5a203a;



	return paravirt_wrmsr_regs(gprs);

}



static inline u64 paravirt_read_tsc(void)

{

arch/x86/include/asm/paravirt_types.h

+0 −2
Original line number Diff line number Diff line
@@ -153,9 +153,7 @@ struct pv_cpu_ops { 
	/* MSR, PMC and TSR operations.

	   err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */

	u64 (*read_msr)(unsigned int msr, int *err);

	int (*rdmsr_regs)(u32 *regs);

	int (*write_msr)(unsigned int msr, unsigned low, unsigned high);

	int (*wrmsr_regs)(u32 *regs);



	u64 (*read_tsc)(void);

	u64 (*read_pmc)(int counter);

arch/x86/kernel/cpu/amd.c

+36 −3
Original line number Diff line number Diff line
@@ -19,6 +19,39 @@ 


#include "cpu.h"



static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)

{

	struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());

	u32 gprs[8] = { 0 };

	int err;



	WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__);



	gprs[1] = msr;

	gprs[7] = 0x9c5a203a;



	err = rdmsr_safe_regs(gprs);



	*p = gprs[0] | ((u64)gprs[2] << 32);



	return err;

}



static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)

{

	struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());

	u32 gprs[8] = { 0 };



	WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__);



	gprs[0] = (u32)val;

	gprs[1] = msr;

	gprs[2] = val >> 32;

	gprs[7] = 0x9c5a203a;



	return wrmsr_safe_regs(gprs);

}



#ifdef CONFIG_X86_32

/*

 *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
@@ -586,9 +619,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 
	    !cpu_has(c, X86_FEATURE_TOPOEXT)) {

		u64 val;



		if (!rdmsrl_amd_safe(0xc0011005, &val)) {

		if (!rdmsrl_safe(0xc0011005, &val)) {

			val |= 1ULL << 54;

			wrmsrl_amd_safe(0xc0011005, val);

			wrmsrl_safe(0xc0011005, val);

			rdmsrl(0xc0011005, val);

			if (val & (1ULL << 54)) {

				set_cpu_cap(c, X86_FEATURE_TOPOEXT);
@@ -679,7 +712,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 
		err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);

		if (err == 0) {

			mask |= (1 << 10);

			checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask);

			wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);

		}

	}

arch/x86/kernel/cpu/common.c

+1 −1
Original line number Diff line number Diff line
@@ -947,7 +947,7 @@ static void __cpuinit __print_cpu_msr(void) 
		index_max = msr_range_array[i].max;



		for (index = index_min; index < index_max; index++) {

			if (rdmsrl_amd_safe(index, &val))

			if (rdmsrl_safe(index, &val))

				continue;

			printk(KERN_INFO " MSR%08x: %016llx\n", index, val);

		}