Commit 715c85b1 authored by H. Peter Anvin's avatar H. Peter Anvin
Browse files

x86, cpu: Rename checking_wrmsrl() to wrmsrl_safe() 



Rename checking_wrmsrl() to wrmsrl_safe(), to match the naming
convention used by all the other MSR access functions/macros.

Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent 2c929ce6

arch/x86/include/asm/msr.h

+1 −1
Original line number Diff line number Diff line
@@ -211,7 +211,7 @@ do { \ 


#endif	/* !CONFIG_PARAVIRT */



#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),		\

#define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val),		\

					     (u32)((val) >> 32))



#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))

arch/x86/kernel/cpu/amd.c

+2 −2
Original line number Diff line number Diff line
@@ -621,7 +621,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 


		if (!rdmsrl_safe(0xc0011005, &val)) {

			val |= 1ULL << 54;

			checking_wrmsrl(0xc0011005, val);

			wrmsrl_safe(0xc0011005, val);

			rdmsrl(0xc0011005, val);

			if (val & (1ULL << 54)) {

				set_cpu_cap(c, X86_FEATURE_TOPOEXT);
@@ -712,7 +712,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) 
		err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);

		if (err == 0) {

			mask |= (1 << 10);

			checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask);

			wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);

		}

	}

arch/x86/kernel/cpu/perf_event.c

+1 −1
Original line number Diff line number Diff line
@@ -222,7 +222,7 @@ static bool check_hw_exists(void) 
	 * that don't trap on the MSR access and always return 0s.

	 */

	val = 0xabcdUL;

	ret = checking_wrmsrl(x86_pmu_event_addr(0), val);

	ret = wrmsrl_safe(x86_pmu_event_addr(0), val);

	ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);

	if (ret || val != val_new)

		goto msr_fail;

arch/x86/kernel/cpu/perf_event_intel.c

+3 −3
Original line number Diff line number Diff line
@@ -1003,11 +1003,11 @@ static void intel_pmu_reset(void) 
	printk("clearing PMU state on CPU#%d\n", smp_processor_id());



	for (idx = 0; idx < x86_pmu.num_counters; idx++) {

		checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);

		checking_wrmsrl(x86_pmu_event_addr(idx),  0ull);

		wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);

		wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);

	}

	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)

		checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);

		wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);



	if (ds)

		ds->bts_index = ds->bts_buffer_base;

arch/x86/kernel/cpu/perf_event_p4.c

+7 −7
Original line number Diff line number Diff line
@@ -895,8 +895,8 @@ static void p4_pmu_disable_pebs(void) 
	 * So at moment let leave metrics turned on forever -- it's

	 * ok for now but need to be revisited!

	 *

	 * (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)0);

	 * (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)0);

	 * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)0);

	 * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)0);

	 */

}
@@ -909,7 +909,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event) 
	 * state we need to clear P4_CCCR_OVF, otherwise interrupt get

	 * asserted again and again

	 */

	(void)checking_wrmsrl(hwc->config_base,

	(void)wrmsrl_safe(hwc->config_base,

		(u64)(p4_config_unpack_cccr(hwc->config)) &

			~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);

}
@@ -943,8 +943,8 @@ static void p4_pmu_enable_pebs(u64 config) 


	bind = &p4_pebs_bind_map[idx];



	(void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE,	(u64)bind->metric_pebs);

	(void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT,	(u64)bind->metric_vert);

	(void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE,	(u64)bind->metric_pebs);

	(void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT,	(u64)bind->metric_vert);

}



static void p4_pmu_enable_event(struct perf_event *event)
@@ -978,8 +978,8 @@ static void p4_pmu_enable_event(struct perf_event *event) 
	 */

	p4_pmu_enable_pebs(hwc->config);



	(void)checking_wrmsrl(escr_addr, escr_conf);

	(void)checking_wrmsrl(hwc->config_base,

	(void)wrmsrl_safe(escr_addr, escr_conf);

	(void)wrmsrl_safe(hwc->config_base,

				(cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE);

}