Commit afcbe252 authored by Bhupesh Sharma's avatar Bhupesh Sharma Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: Fix 'reg-names' for sdhci nodes 



Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'reg-names' as various possible combinations
are possible for different qcom SoC dts files.

Fix the same by updating the offending 'dts' files.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: default avatarBhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-6-bhupesh.sharma@linaro.org
parent 4ff12270

arch/arm64/boot/dts/qcom/qcs404.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -809,7 +809,7 @@ 
		sdcc1: mmc@7804000 {

			compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";

			reg = <0x07804000 0x1000>, <0x7805000 0x1000>;

			reg-names = "hc", "cqhci";

			reg-names = "hc_mem", "cqe_mem";



			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/sc7180.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -697,7 +697,7 @@ 
			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";

			reg = <0 0x7c4000 0 0x1000>,

				<0 0x07c5000 0 0x1000>;

			reg-names = "hc", "cqhci";

			reg-names = "hc_mem", "cqe_mem";



			iommus = <&apps_smmu 0x60 0x0>;

			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/qcom/sc7280.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -866,7 +866,7 @@ 


			reg = <0 0x007c4000 0 0x1000>,

			      <0 0x007c5000 0 0x1000>;

			reg-names = "hc", "cqhci";

			reg-names = "hc_mem", "cqe_mem";



			iommus = <&apps_smmu 0xc0 0x0>;

			interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/qcom/sdm630.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1280,7 +1280,7 @@ 
		sdhc_2: mmc@c084000 {

			compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";

			reg = <0x0c084000 0x1000>;

			reg-names = "hc";

			reg-names = "hc_mem";



			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
@@ -1335,7 +1335,7 @@ 
			reg = <0x0c0c4000 0x1000>,

			      <0x0c0c5000 0x1000>,

			      <0x0c0c8000 0x8000>;

			reg-names = "hc", "cqhci", "ice";

			reg-names = "hc_mem", "cqe_mem", "ice_mem";



			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/sm6125.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -438,7 +438,7 @@ 
		sdhc_1: mmc@4744000 {

			compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";

			reg = <0x04744000 0x1000>, <0x04745000 0x1000>;

			reg-names = "hc", "core";

			reg-names = "hc_mem", "core_mem";



			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -459,7 +459,7 @@ 
		sdhc_2: mmc@4784000 {

			compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";

			reg = <0x04784000 0x1000>;

			reg-names = "hc";

			reg-names = "hc_mem";



			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;