Commit 4ff12270 authored by Bhupesh Sharma's avatar Bhupesh Sharma Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names' for sdhci nodes 



Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports a number of issues with
ordering of 'clocks' & 'clock-names' for sdhci nodes:

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:0: 'iface' was expected

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:1: 'core' was expected

 arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  clock-names:2: 'xo' was expected

Fix the same by updating the offending 'dts' files.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: default avatarBhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org
parent 40940823

arch/arm64/boot/dts/qcom/ipq8074.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -384,10 +384,10 @@ 
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";



			clocks = <&xo>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>;

			clock-names = "xo", "iface", "core";

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&xo>;

			clock-names = "iface", "core", "xo";

			max-frequency = <384000000>;

			mmc-ddr-1_8v;

			mmc-hs200-1_8v;

arch/arm64/boot/dts/qcom/msm8916.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -1472,10 +1472,10 @@ 
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			mmc-ddr-1_8v;

			bus-width = <8>;

			non-removable;
@@ -1490,10 +1490,10 @@ 
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,

				 <&gcc GCC_SDCC2_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			bus-width = <4>;

			status = "disabled";

		};

arch/arm64/boot/dts/qcom/msm8994.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -470,10 +470,10 @@ 
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";



			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

			         <&gcc GCC_SDCC1_AHB_CLK>,

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";



			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
@@ -493,10 +493,10 @@ 
				<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";



			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				<&gcc GCC_SDCC2_AHB_CLK>,

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,

				 <&gcc GCC_SDCC2_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";



			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;

arch/arm64/boot/dts/qcom/qcs404.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -815,10 +815,10 @@ 
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";



			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&xo_board>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";



			status = "disabled";

		};

arch/arm64/boot/dts/qcom/sc7180.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -704,10 +704,10 @@ 
					<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";



			clocks = <&gcc GCC_SDCC1_APPS_CLK>,

				 <&gcc GCC_SDCC1_AHB_CLK>,

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,

				 <&gcc GCC_SDCC1_APPS_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";

			interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,

					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;

			interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -2587,10 +2587,10 @@ 
					<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hc_irq", "pwr_irq";



			clocks = <&gcc GCC_SDCC2_APPS_CLK>,

				 <&gcc GCC_SDCC2_AHB_CLK>,

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,

				 <&gcc GCC_SDCC2_APPS_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "core", "iface", "xo";

			clock-names = "iface", "core", "xo";



			interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,

					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;