Commit ae9b24dd authored by Danielle Ratson's avatar Danielle Ratson Committed by Jakub Kicinski
Browse files

mlxsw: spectrum_ethtool: Add an external speed to PTYS register 



Currently, only external bits are added to the PTYS register, whereas
there is one external bit that is wrongly marked as internal, and so was
recently removed from the register.

Add that bit to the PTYS register again, as this bit is no longer
internal.

Its removal resulted in '100000baseLR4_ER4/Full' link mode no longer
being supported, causing a regression on some setups.

Fixes: 5bf01b57 ("mlxsw: spectrum_ethtool: Remove internal speeds from PTYS register")
Signed-off-by: default avatarDanielle Ratson <danieller@nvidia.com>
Reported-by: default avatarEddie Shklaer <eddies@nvidia.com>
Tested-by: default avatarEddie Shklaer <eddies@nvidia.com>
Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
Signed-off-by: default avatarIdo Schimmel <idosch@nvidia.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent edcbf513

drivers/net/ethernet/mellanox/mlxsw/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4430,6 +4430,7 @@ MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 
#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4		BIT(20)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4		BIT(21)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4		BIT(22)

#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4	BIT(23)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR		BIT(27)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR		BIT(28)

#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR		BIT(29)

drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c

+5 −0
Original line number Diff line number Diff line
@@ -1169,6 +1169,11 @@ static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = { 
		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,

		.speed		= SPEED_100000,

	},

	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,

		.mask_ethtool	= ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,

		.speed		= SPEED_100000,

	},

};



#define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)

drivers/net/ethernet/mellanox/mlxsw/switchx2.c

+2 −1
Original line number Diff line number Diff line
@@ -613,7 +613,8 @@ static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = { 
	{

		.mask		= MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |

				  MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,

		.speed		= 100000,

	},

};