Commit ae02d415 authored by Eran Ben Elisha's avatar Eran Ben Elisha Committed by Saeed Mahameed
Browse files

net/mlx5: Add register layout to support real-time time-stamp 



Add needed structure layouts and defines for MTUTC (Management UTC)
register. MTUTC will be used for cyc2time HW translation.

In addition, add cyc2time modify capability bit and init segment HCA
real time address.

Finally, add capability bits indicating which time-stamping format is
supported per SQ and RQ. Add ts_format in the queue's context layout to
allow configuration.

Signed-off-by: default avatarEran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: default avatarAya Levin <ayal@nvidia.com>
Reviewed-by: default avatarMoshe Shemesh <moshe@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent a6a217dd

include/linux/mlx5/device.h

+4 −1
Original line number Diff line number Diff line
@@ -578,7 +578,10 @@ struct mlx5_init_seg { 
	__be32			internal_timer_l;

	__be32			rsvd3[2];

	__be32			health_counter;

	__be32			rsvd4[1019];

	__be32			rsvd4[11];

	__be32			real_time_h;

	__be32			real_time_l;

	__be32			rsvd5[1006];

	__be64			ieee1588_clk;

	__be32			ieee1588_clk_type;

	__be32			clr_intx;

include/linux/mlx5/driver.h

+1 −0
Original line number Diff line number Diff line
@@ -143,6 +143,7 @@ enum { 
	MLX5_REG_MPCNT		 = 0x9051,

	MLX5_REG_MTPPS		 = 0x9053,

	MLX5_REG_MTPPSE		 = 0x9054,

	MLX5_REG_MTUTC		 = 0x9055,

	MLX5_REG_MPEGC		 = 0x9056,

	MLX5_REG_MCQS		 = 0x9060,

	MLX5_REG_MCQI		 = 0x9061,

include/linux/mlx5/mlx5_ifc.h

+28 −2
Original line number Diff line number Diff line
@@ -9150,6 +9150,28 @@ struct mlx5_ifc_mpegc_reg_bits { 
	u8         reserved_at_60[0x100];

};



enum {

	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,

	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,

	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,

};



struct mlx5_ifc_mtutc_reg_bits {

	u8         reserved_at_0[0x1c];

	u8         operation[0x4];



	u8         freq_adjustment[0x20];



	u8         reserved_at_40[0x40];



	u8         utc_sec[0x20];



	u8         reserved_at_a0[0x2];

	u8         utc_nsec[0x1e];



	u8         time_adjustment[0x20];

};



struct mlx5_ifc_pcam_enhanced_features_bits {

	u8         reserved_at_0[0x68];

	u8         fec_50G_per_lane_in_pplm[0x1];
@@ -9208,7 +9230,9 @@ struct mlx5_ifc_pcam_reg_bits { 
};



struct mlx5_ifc_mcam_enhanced_features_bits {

	u8         reserved_at_0[0x6e];

	u8         reserved_at_0[0x6b];

	u8         ptpcyc2realtime_modify[0x1];

	u8         reserved_at_6c[0x2];

	u8         pci_status_and_power[0x1];

	u8         reserved_at_6f[0x5];

	u8         mark_tx_action_cnp[0x1];
@@ -9231,7 +9255,8 @@ struct mlx5_ifc_mcam_access_reg_bits { 


	u8         regs_95_to_87[0x9];

	u8         mpegc[0x1];

	u8         regs_85_to_68[0x12];

	u8         mtutc[0x1];

	u8         regs_84_to_68[0x11];

	u8         tracer_registers[0x4];



	u8         regs_63_to_32[0x20];
@@ -9964,6 +9989,7 @@ union mlx5_ifc_ports_control_registers_document_bits { 
	struct mlx5_ifc_mcda_reg_bits mcda_reg;

	struct mlx5_ifc_mirc_reg_bits mirc_reg;

	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;

	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;

	u8         reserved_at_0[0x60e0];

};