Commit a6a217dd authored by Aharon Landau's avatar Aharon Landau Committed by Leon Romanovsky
Browse files

net/mlx5: Add new timestamp mode bits 

These fields declare which timestamp mode is supported by the device
per RQ/SQ/QP.

In addition add the ts_format field to the select the mode for
RQ/SQ/QP.

Link: https://lore.kernel.org/r/20210209131107.698833-2-leon@kernel.org


Signed-off-by: default avatarAharon Landau <aharonl@nvidia.com>
Signed-off-by: default avatarMaor Gottlieb <maorg@nvidia.com>
Signed-off-by: default avatarLeon Romanovsky <leonro@nvidia.com>
parent ab0da5a5

include/linux/mlx5/mlx5_ifc.h

+49 −5
Original line number Diff line number Diff line
@@ -932,11 +932,18 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 
	u8         reserved_at_200[0x600];

};



enum {

	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,

	MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,

	MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,

};



struct mlx5_ifc_roce_cap_bits {

	u8         roce_apm[0x1];

	u8         reserved_at_1[0x3];

	u8         sw_r_roce_src_udp_port[0x1];

	u8         reserved_at_5[0x1b];

	u8         reserved_at_5[0x19];

	u8	   qp_ts_format[0x2];



	u8         reserved_at_20[0x60];
@@ -1253,6 +1260,18 @@ enum { 
	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,

};



enum {

	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,

	MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,

	MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,

};



enum {

	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,

	MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,

	MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,

};



struct mlx5_ifc_cmd_hca_cap_bits {

	u8         reserved_at_0[0x1f];

	u8         vhca_resource_manager[0x1];
@@ -1564,7 +1583,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { 


	u8         general_obj_types[0x40];



	u8         reserved_at_440[0x4];

	u8         sq_ts_format[0x2];

	u8         rq_ts_format[0x2];

	u8         steering_format_version[0x4];

	u8         create_qp_start_hint[0x18];
@@ -2868,6 +2888,12 @@ enum { 
	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,

};



enum {

	MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,

	MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,

	MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,

};



struct mlx5_ifc_qpc_bits {

	u8         state[0x4];

	u8         lag_tx_port_affinity[0x4];
@@ -2896,7 +2922,9 @@ struct mlx5_ifc_qpc_bits { 
	u8         log_rq_stride[0x3];

	u8         no_sq[0x1];

	u8         log_sq_size[0x4];

	u8         reserved_at_55[0x6];

	u8         reserved_at_55[0x3];

	u8	   ts_format[0x2];

	u8         reserved_at_5a[0x1];

	u8         rlky[0x1];

	u8         ulp_stateless_offload_mode[0x4];
@@ -3312,6 +3340,12 @@ enum { 
	MLX5_SQC_STATE_ERR  = 0x3,

};



enum {

	MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,

	MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,

	MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,

};



struct mlx5_ifc_sqc_bits {

	u8         rlky[0x1];

	u8         cd_master[0x1];
@@ -3323,7 +3357,9 @@ struct mlx5_ifc_sqc_bits { 
	u8         reg_umr[0x1];

	u8         allow_swp[0x1];

	u8         hairpin[0x1];

	u8         reserved_at_f[0x11];

	u8         reserved_at_f[0xb];

	u8	   ts_format[0x2];

	u8	   reserved_at_1c[0x4];



	u8         reserved_at_20[0x8];

	u8         user_index[0x18];
@@ -3414,6 +3450,12 @@ enum { 
	MLX5_RQC_STATE_ERR  = 0x3,

};



enum {

	MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,

	MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,

	MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,

};



struct mlx5_ifc_rqc_bits {

	u8         rlky[0x1];

	u8	   delay_drop_en[0x1];
@@ -3424,7 +3466,9 @@ struct mlx5_ifc_rqc_bits { 
	u8         reserved_at_c[0x1];

	u8         flush_in_error_en[0x1];

	u8         hairpin[0x1];

	u8         reserved_at_f[0x11];

	u8         reserved_at_f[0xb];

	u8	   ts_format[0x2];

	u8	   reserved_at_1c[0x4];



	u8         reserved_at_20[0x8];

	u8         user_index[0x18];