Unverified Commit ac94e68b authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!525 net: hns3: add supports storage product scustomization requirements 

Merge Pull Request from: @svishen 
 
The PR incorporates the customization code framework to support hns3 customization requirements. The following functions are supported:

1.add support check whether the network port device is HNS3
2.add support clear mac statistics
3.add support configuring function-level interrupt affinity
4.add supports pfc storm detection and suppression
5.add support query port ext information
6.add supports fast reporting of faulty nodes
7.add support to get/set 1d torus param
8.add support customized exception handling interfaces

issue:
https://gitee.com/openeuler/kernel/issues/I6QRKC 
 
Link:https://gitee.com/openeuler/kernel/pulls/525

 

Reviewed-by: default avatarYue Haibing <yuehaibing@huawei.com>
Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents b804f73d 0a8ca728

drivers/net/ethernet/hisilicon/hns3/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ obj-$(CONFIG_HNS3) += hnae3.o 


obj-$(CONFIG_HNS3_ENET) += hns3.o

hns3-objs = hns3_enet.o hns3_ethtool.o hns3_debugfs.o

hns3-objs += hns3_ext.o



hns3-$(CONFIG_HNS3_DCB) += hns3_dcbnl.o
@@ -24,6 +25,6 @@ obj-$(CONFIG_HNS3_HCLGE) += hclge.o 
hclge-objs = hns3pf/hclge_main.o hns3pf/hclge_mdio.o hns3pf/hclge_tm.o hns3pf/hclge_sysfs.o \

		hns3pf/hclge_mbx.o hns3pf/hclge_err.o  hns3pf/hclge_debugfs.o hns3pf/hclge_ptp.o hns3pf/hclge_devlink.o \

		hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o



hclge-objs += hns3pf/hclge_ext.o



hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+6 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ enum HNAE3_DEV_CAP_BITS { 
	HNAE3_DEV_SUPPORT_LANE_NUM_B,

	HNAE3_DEV_SUPPORT_WOL_B,

	HNAE3_DEV_SUPPORT_VF_FAULT_B,

	HNAE3_DEV_SUPPORT_NOTIFY_PKT_B,

};



#define hnae3_ae_dev_fd_supported(ae_dev) \
@@ -174,6 +175,9 @@ enum HNAE3_DEV_CAP_BITS { 
#define hnae3_ae_dev_vf_fault_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_VF_FAULT_B, (ae_dev)->caps)



#define hnae3_ae_dev_notify_pkt_supported(ae_dev) \

	test_bit(HNAE3_DEV_SUPPORT_NOTIFY_PKT_B, (ae_dev)->caps)



enum HNAE3_PF_CAP_BITS {

	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,

};
@@ -785,6 +789,8 @@ struct hnae3_ae_ops { 
			struct ethtool_wolinfo *wol);

	int (*set_wol)(struct hnae3_handle *handle,

		       struct ethtool_wolinfo *wol);

	int (*priv_ops)(struct hnae3_handle *handle, int opcode,

			void *data, size_t length);

};



struct hnae3_dcb_ops {

drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h

0 → 100644
+75 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */

// Copyright (c) 2023 Hisilicon Limited.



#ifndef __HNAE3_EXT_H

#define __HNAE3_EXT_H



enum hnae3_event_type_custom {

	HNAE3_VF_RESET_CUSTOM,

	HNAE3_VF_FUNC_RESET_CUSTOM,

	HNAE3_VF_PF_FUNC_RESET_CUSTOM,

	HNAE3_VF_FULL_RESET_CUSTOM,

	HNAE3_FLR_RESET_CUSTOM,

	HNAE3_FUNC_RESET_CUSTOM,

	HNAE3_GLOBAL_RESET_CUSTOM,

	HNAE3_IMP_RESET_CUSTOM,

	HNAE3_UNKNOWN_RESET_CUSTOM,

	HNAE3_NONE_RESET_CUSTOM,

	HNAE3_PORT_FAULT,

	HNAE3_RESET_DONE_CUSTOM,

	HNAE3_FUNC_RESET_FAIL_CUSTOM,

	HNAE3_GLOBAL_RESET_FAIL_CUSTOM,

	HNAE3_IMP_RESET_FAIL_CUSTOM,

	HNAE3_PPU_POISON_CUSTOM,

	HNAE3_IMP_RD_POISON_CUSTOM,

	HNAE3_INVALID_EVENT_CUSTOM,

};



enum hnae3_ext_opcode {

	HNAE3_EXT_OPC_RESET,

	HNAE3_EXT_OPC_EVENT_CALLBACK,

	HNAE3_EXT_OPC_GET_PFC_STORM_PARA,

	HNAE3_EXT_OPC_SET_PFC_STORM_PARA,

	HNAE3_EXT_OPC_SET_NOTIFY_PARAM,

	HNAE3_EXT_OPC_SET_NOTIFY_START,

	HNAE3_EXT_OPC_SET_TORUS_PARAM,

	HNAE3_EXT_OPC_GET_TORUS_PARAM,

	HNAE3_EXT_OPC_CLEAN_STATS64,

	HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO,

	HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO,

	HNAE3_EXT_OPC_GET_PORT_NUM,

};



struct hnae3_pfc_storm_para {

	u32 dir;

	u32 enable;

	u32 period_ms;

	u32 times;

	u32 recovery_period_ms;

};



struct hnae3_notify_pkt_param {

	u32 ipg;     /* inter-packet gap of sending, the unit is one cycle of clock */

	u16 num;     /* packet number of sending */

	u8 enable;   /* send enable, 0=Disable, 1=Enable */

	u8 init;     /* initialization flag, product does not need to set value */

	u8 data[64]; /* note packet data */

};



struct hnae3_torus_param {

	u32 enable;       /* 1d torus mode enable */

	u32 mac_id;       /* export mac id of port */

	u8 is_node0;      /* if current node is node0 */

};



struct hane3_port_ext_id_info {

	u32 chip_id;

	u32 mac_id;

	u32 io_die_id;

};



struct hane3_port_ext_num_info {

	u32 chip_num;

	u32 io_die_num;

};

#endif

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = { 
	{HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B},

	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},

	{HCLGE_COMM_CAP_VF_FAULT_B, HNAE3_DEV_SUPPORT_VF_FAULT_B},

	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},

};



static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {

drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h

+1 −0
Original line number Diff line number Diff line
@@ -348,6 +348,7 @@ enum HCLGE_COMM_CAP_BITS { 
	HCLGE_COMM_CAP_VF_FAULT_B = 26,

	HCLGE_COMM_CAP_LANE_NUM_B = 27,

	HCLGE_COMM_CAP_WOL_B = 28,

	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,

};



enum HCLGE_COMM_API_CAP_BITS {