Unverified Commit b804f73d authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!519 Add new command to support query vf caps 

Merge Pull Request from: @stinft 
 
The current resource query for vf caps is driven by the driver, which is unreasonable. This patch adds a new command HNS_ROCE_OPC_QUERY_PF_CAPS_NUM to support obtaining vf caps information from firmware.
bugzilla:#I6K9B6 
 
Link:https://gitee.com/openeuler/kernel/pulls/519

 

Reviewed-by: default avatarChengchang Tang <tangchengchang@huawei.com>
Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Reviewed-by: default avatarYue Haibing <yuehaibing@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents b532c5d3 1890b7dd

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+62 −141
Original line number Diff line number Diff line
@@ -2157,102 +2157,6 @@ static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) 
	return hns_roce_cmq_send(hr_dev, &desc, 1);

}



/* Use default caps when hns_roce_query_pf_caps() failed or init VF profile */

static void set_default_caps(struct hns_roce_dev *hr_dev)

{

	struct hns_roce_caps *caps = &hr_dev->caps;



	caps->num_qps		= HNS_ROCE_V2_MAX_QP_NUM;

	caps->max_wqes		= HNS_ROCE_V2_MAX_WQE_NUM;

	caps->num_cqs		= HNS_ROCE_V2_MAX_CQ_NUM;

	caps->num_srqs		= HNS_ROCE_V2_MAX_SRQ_NUM;

	caps->min_cqes		= HNS_ROCE_MIN_CQE_NUM;

	caps->max_cqes		= HNS_ROCE_V2_MAX_CQE_NUM;

	caps->max_sq_sg		= HNS_ROCE_V2_MAX_SQ_SGE_NUM;

	caps->max_extend_sg	= HNS_ROCE_V2_MAX_EXTEND_SGE_NUM;

	caps->max_rq_sg		= HNS_ROCE_V2_MAX_RQ_SGE_NUM;



	caps->num_uars		= HNS_ROCE_V2_UAR_NUM;

	caps->phy_num_uars	= HNS_ROCE_V2_PHY_UAR_NUM;

	caps->num_aeq_vectors	= HNS_ROCE_V2_AEQE_VEC_NUM;

	caps->num_other_vectors = HNS_ROCE_V2_ABNORMAL_VEC_NUM;

	caps->num_comp_vectors	= 0;



	caps->num_mtpts		= HNS_ROCE_V2_MAX_MTPT_NUM;

	caps->num_pds		= HNS_ROCE_V2_MAX_PD_NUM;

	caps->num_qpc_timer	= HNS_ROCE_V2_MAX_QPC_TIMER_NUM;

	caps->cqc_timer_bt_num	= HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM;



	caps->max_qp_init_rdma	= HNS_ROCE_V2_MAX_QP_INIT_RDMA;

	caps->max_qp_dest_rdma	= HNS_ROCE_V2_MAX_QP_DEST_RDMA;

	caps->max_sq_desc_sz	= HNS_ROCE_V2_MAX_SQ_DESC_SZ;

	caps->max_rq_desc_sz	= HNS_ROCE_V2_MAX_RQ_DESC_SZ;

	caps->max_srq_desc_sz	= HNS_ROCE_V2_MAX_SRQ_DESC_SZ;

	caps->irrl_entry_sz	= HNS_ROCE_V2_IRRL_ENTRY_SZ;

	caps->trrl_entry_sz	= HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ;

	caps->cqc_entry_sz	= HNS_ROCE_V2_CQC_ENTRY_SZ;

	caps->srqc_entry_sz	= HNS_ROCE_V2_SRQC_ENTRY_SZ;

	caps->mtpt_entry_sz	= HNS_ROCE_V2_MTPT_ENTRY_SZ;

	caps->idx_entry_sz	= HNS_ROCE_V2_IDX_ENTRY_SZ;

	caps->page_size_cap	= HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;

	caps->reserved_lkey	= 0;

	caps->reserved_pds	= 0;

	caps->reserved_mrws	= 1;

	caps->reserved_uars	= 0;

	caps->reserved_cqs	= 0;

	caps->reserved_srqs	= 0;

	caps->reserved_qps	= HNS_ROCE_V2_RSV_QPS;



	caps->qpc_hop_num	= HNS_ROCE_CONTEXT_HOP_NUM;

	caps->srqc_hop_num	= HNS_ROCE_CONTEXT_HOP_NUM;

	caps->cqc_hop_num	= HNS_ROCE_CONTEXT_HOP_NUM;

	caps->mpt_hop_num	= HNS_ROCE_CONTEXT_HOP_NUM;

	caps->sccc_hop_num	= HNS_ROCE_SCCC_HOP_NUM;



	caps->mtt_hop_num	= HNS_ROCE_MTT_HOP_NUM;

	caps->wqe_sq_hop_num	= HNS_ROCE_SQWQE_HOP_NUM;

	caps->wqe_sge_hop_num	= HNS_ROCE_EXT_SGE_HOP_NUM;

	caps->wqe_rq_hop_num	= HNS_ROCE_RQWQE_HOP_NUM;

	caps->cqe_hop_num	= HNS_ROCE_CQE_HOP_NUM;

	caps->srqwqe_hop_num	= HNS_ROCE_SRQWQE_HOP_NUM;

	caps->idx_hop_num	= HNS_ROCE_IDX_HOP_NUM;

	caps->chunk_sz          = HNS_ROCE_V2_TABLE_CHUNK_SIZE;



	caps->flags		= HNS_ROCE_CAP_FLAG_REREG_MR |

				  HNS_ROCE_CAP_FLAG_ROCE_V1_V2 |

				  HNS_ROCE_CAP_FLAG_CQ_RECORD_DB |

				  HNS_ROCE_CAP_FLAG_QP_RECORD_DB;



	caps->pkey_table_len[0] = 1;

	caps->ceqe_depth	= HNS_ROCE_V2_COMP_EQE_NUM;

	caps->aeqe_depth	= HNS_ROCE_V2_ASYNC_EQE_NUM;

	caps->local_ca_ack_delay = 0;

	caps->max_mtu = IB_MTU_4096;



	caps->max_srq_wrs	= HNS_ROCE_V2_MAX_SRQ_WR;

	caps->max_srq_sges	= HNS_ROCE_V2_MAX_SRQ_SGE;



	caps->flags |= HNS_ROCE_CAP_FLAG_ATOMIC | HNS_ROCE_CAP_FLAG_MW |

		       HNS_ROCE_CAP_FLAG_SRQ | HNS_ROCE_CAP_FLAG_FRMR |

		       HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL | HNS_ROCE_CAP_FLAG_XRC;



	caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;



	if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {

		caps->flags |= HNS_ROCE_CAP_FLAG_STASH |

			       HNS_ROCE_CAP_FLAG_DIRECT_WQE |

			       HNS_ROCE_CAP_FLAG_DCA_MODE;

		caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE;

	} else {

		caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE;



		/* The following configuration are only valid for HIP08 */

		caps->qpc_sz = HNS_ROCE_V2_QPC_SZ;

		caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ;

		caps->cqe_sz = HNS_ROCE_V2_CQE_SIZE;

	}

}



static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num,

		       u32 *buf_page_size, u32 *bt_page_size, u32 hem_type)

{
@@ -2395,7 +2299,8 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev) 


	if (!caps->num_comp_vectors)

		caps->num_comp_vectors = min_t(u32, caps->eqc_bt_num - 1,

				  (u32)priv->handle->rinfo.num_vectors - 2);

				  (u32)priv->handle->rinfo.num_vectors -

		(HNS_ROCE_V2_AEQE_VEC_NUM + HNS_ROCE_V2_ABNORMAL_VEC_NUM));



	if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {

		caps->eqe_hop_num = HNS_ROCE_V3_EQE_HOP_NUM;
@@ -2437,7 +2342,7 @@ static void apply_func_caps(struct hns_roce_dev *hr_dev) 
	set_hem_page_size(hr_dev);

}



static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)

static int hns_roce_query_caps(struct hns_roce_dev *hr_dev)

{

	struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];

	struct hns_roce_caps *caps = &hr_dev->caps;
@@ -2446,15 +2351,17 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 
	struct hns_roce_query_pf_caps_c *resp_c;

	struct hns_roce_query_pf_caps_d *resp_d;

	struct hns_roce_query_pf_caps_e *resp_e;

	enum hns_roce_opcode_type cmd;

	int ctx_hop_num;

	int pbl_hop_num;

	int ret;

	int i;



	cmd = hr_dev->is_vf ? HNS_ROCE_OPC_QUERY_VF_CAPS_NUM :

	      HNS_ROCE_OPC_QUERY_PF_CAPS_NUM;



	for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {

		hns_roce_cmq_setup_basic_desc(&desc[i],

					      HNS_ROCE_OPC_QUERY_PF_CAPS_NUM,

					      true);

		hns_roce_cmq_setup_basic_desc(&desc[i], cmd, true);

		if (i < (HNS_ROCE_QUERY_PF_CAPS_CMD_NUM - 1))

			desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);

		else
@@ -2525,8 +2432,6 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 
	caps->ceqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_CEQ_DEPTH);

	caps->num_comp_vectors = hr_reg_read(resp_d, PF_CAPS_D_NUM_CEQS);

	caps->aeqe_depth = 1 << hr_reg_read(resp_d, PF_CAPS_D_AEQ_DEPTH);

	caps->default_aeq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);

	caps->default_ceq_arm_st = hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);

	caps->reserved_pds = hr_reg_read(resp_d, PF_CAPS_D_RSV_PDS);

	caps->num_uars = 1 << hr_reg_read(resp_d, PF_CAPS_D_NUM_UARS);

	caps->reserved_qps = hr_reg_read(resp_d, PF_CAPS_D_RSV_QPS);
@@ -2537,10 +2442,6 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 
	caps->reserved_cqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_CQS);

	caps->reserved_srqs = hr_reg_read(resp_e, PF_CAPS_E_RSV_SRQS);

	caps->reserved_lkey = hr_reg_read(resp_e, PF_CAPS_E_RSV_LKEYS);

	caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);

	caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);

	caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);

	caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);



	caps->qpc_hop_num = ctx_hop_num;

	caps->sccc_hop_num = ctx_hop_num;
@@ -2557,6 +2458,20 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 


	if (!(caps->page_size_cap & PAGE_SIZE))

		caps->page_size_cap = HNS_ROCE_V2_PAGE_SIZE_SUPPORTED;



	if (!hr_dev->is_vf) {

		caps->cqe_sz = resp_a->cqe_sz;

		caps->qpc_sz = le16_to_cpu(resp_b->qpc_sz);

		caps->default_aeq_arm_st =

				hr_reg_read(resp_d, PF_CAPS_D_AEQ_ARM_ST);

		caps->default_ceq_arm_st =

				hr_reg_read(resp_d, PF_CAPS_D_CEQ_ARM_ST);

		caps->default_ceq_max_cnt = le16_to_cpu(resp_e->ceq_max_cnt);

		caps->default_ceq_period = le16_to_cpu(resp_e->ceq_period);

		caps->default_aeq_max_cnt = le16_to_cpu(resp_e->aeq_max_cnt);

		caps->default_aeq_period = le16_to_cpu(resp_e->aeq_period);

	}



	return 0;

}
@@ -2626,7 +2541,11 @@ static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) 


	hr_dev->func_num = 1;



	set_default_caps(hr_dev);

	ret = hns_roce_query_caps(hr_dev);

	if (ret) {

		dev_err(dev, "failed to query VF caps, ret = %d.\n", ret);

		return ret;

	}



	ret = hns_roce_query_vf_resource(hr_dev);

	if (ret) {
@@ -2666,9 +2585,11 @@ static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) 
		return ret;

	}



	ret = hns_roce_query_pf_caps(hr_dev);

	if (ret)

		set_default_caps(hr_dev);

	ret = hns_roce_query_caps(hr_dev);

	if (ret) {

		dev_err(dev, "failed to query PF caps, ret = %d.\n", ret);

		return ret;

	}



	ret = hns_roce_query_pf_resource(hr_dev);

	if (ret) {

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+2 −31
Original line number Diff line number Diff line
@@ -35,46 +35,16 @@ 


#include <linux/bitops.h>



#define HNS_ROCE_V2_MAX_QP_NUM			0x1000

#define HNS_ROCE_V2_MAX_QPC_TIMER_NUM		0x200

#define HNS_ROCE_V2_MAX_WQE_NUM			0x8000

#define HNS_ROCE_V2_MAX_SRQ_WR			0x8000

#define HNS_ROCE_V2_MAX_SRQ_SGE			64

#define HNS_ROCE_V2_MAX_CQ_NUM			0x100000

#define HNS_ROCE_V2_MAX_CQC_TIMER_BT_NUM	0x100

#define HNS_ROCE_V2_MAX_SRQ_NUM			0x100000

#define HNS_ROCE_V2_MAX_CQE_NUM			0x400000

#define HNS_ROCE_V2_MAX_RQ_SGE_NUM		64

#define HNS_ROCE_V2_MAX_SQ_SGE_NUM		64

#define HNS_ROCE_V2_MAX_EXTEND_SGE_NUM		0x200000

#define HNS_ROCE_V2_MAX_SQ_INLINE		0x20

#define HNS_ROCE_V3_MAX_SQ_INLINE		0x400

#define HNS_ROCE_V2_MAX_RC_INL_INN_SZ		32

#define HNS_ROCE_V2_UAR_NUM			256

#define HNS_ROCE_V2_PHY_UAR_NUM			1

#define HNS_ROCE_V2_MTT_ENTRY_SZ		64

#define HNS_ROCE_V2_AEQE_VEC_NUM		1

#define HNS_ROCE_V2_ABNORMAL_VEC_NUM		1

#define HNS_ROCE_V2_MAX_MTPT_NUM		0x100000

#define HNS_ROCE_V2_MAX_MTT_SEGS		0x1000000

#define HNS_ROCE_V2_MAX_SRQWQE_SEGS		0x1000000

#define HNS_ROCE_V2_MAX_IDX_SEGS		0x1000000

#define HNS_ROCE_V2_MAX_PD_NUM			0x1000000

#define HNS_ROCE_V2_MAX_XRCD_NUM		0x1000000

#define HNS_ROCE_V2_RSV_XRCD_NUM		0

#define HNS_ROCE_V2_MAX_QP_INIT_RDMA		128

#define HNS_ROCE_V2_MAX_QP_DEST_RDMA		128

#define HNS_ROCE_V2_MAX_SQ_DESC_SZ		64

#define HNS_ROCE_V2_MAX_RQ_DESC_SZ		16

#define HNS_ROCE_V2_MAX_SRQ_DESC_SZ		64

#define HNS_ROCE_V2_IRRL_ENTRY_SZ		64

#define HNS_ROCE_V2_EXT_ATOMIC_TRRL_ENTRY_SZ	100

#define HNS_ROCE_V2_CQC_ENTRY_SZ		64

#define HNS_ROCE_V2_SRQC_ENTRY_SZ		64

#define HNS_ROCE_V2_MTPT_ENTRY_SZ		64

#define HNS_ROCE_V2_MTT_ENTRY_SZ		64

#define HNS_ROCE_V2_IDX_ENTRY_SZ		4



#define HNS_ROCE_V2_SCCC_SZ			32

#define HNS_ROCE_V3_SCCC_SZ			64

#define HNS_ROCE_V3_GMV_ENTRY_SZ		32
@@ -242,6 +212,7 @@ enum hns_roce_opcode_type { 
	HNS_ROCE_OPC_QUERY_FUNC_INFO			= 0x8407,

	HNS_ROCE_OPC_QUERY_PF_CAPS_NUM                  = 0x8408,

	HNS_ROCE_OPC_CFG_ENTRY_SIZE			= 0x8409,

	HNS_ROCE_OPC_QUERY_VF_CAPS_NUM			= 0x8410,

	HNS_ROCE_OPC_CFG_SGID_TB			= 0x8500,

	HNS_ROCE_OPC_CFG_SMAC_TB			= 0x8501,

	HNS_ROCE_OPC_POST_MB				= 0x8504,