Commit ab291621 authored by Conor Dooley's avatar Conor Dooley
Browse files

riscv: dts: microchip: icicle: re-jig fabric peripheral addresses 



When users try to add onto the reference design, they find that the
current addresses that peripherals connected to Fabric InterConnect
(FIC) 3 use are restrictive. For the v2022.09 reference design, the
peripherals have been shifted down, leaving more contiguous address
space for their custom IP/peripherals.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 6fc655ed

arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -5,18 +5,18 @@ 
	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",

		     "microchip,mpfs";



	core_pwm0: pwm@41000000 {

	core_pwm0: pwm@40000000 {

		compatible = "microchip,corepwm-rtl-v4";

		reg = <0x0 0x41000000 0x0 0xF0>;

		reg = <0x0 0x40000000 0x0 0xF0>;

		microchip,sync-update-mask = /bits/ 32 <0>;

		#pwm-cells = <2>;

		clocks = <&fabric_clk3>;

		status = "disabled";

	};



	i2c2: i2c@44000000 {

	i2c2: i2c@40000200 {

		compatible = "microchip,corei2c-rtl-v7";

		reg = <0x0 0x44000000 0x0 0x1000>;

		reg = <0x0 0x40000200 0x0 0x1000>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&fabric_clk3>;