Commit ab076d8d authored Jan 10, 2022 by Matt Roper

drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7

It's preferable to use parameterized register macros where possible.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-6-matthew.d.roper@intel.com

parent 3e5cbecb

drivers/gpu/drm/i915/gt/intel_workarounds.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2013,7 +2013,7 @@ rcs_engine_wa_init(struct intel_engine_cs engine, struct i915_wa_list wal)
		if (GRAPHICS_VER(i915) == 7) {
		/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
		wa_masked_en(wal,
		GFX_MODE_GEN7,
		RING_MODE_GEN7(RENDER_RING_BASE),
		GFX_TLB_INVALIDATE_EXPLICIT \| GFX_REPLAY_MODE);

		/* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */

drivers/gpu/drm/i915/gvt/mmio_context.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -44,7 +44,7 @@

		/* Raw offset is appened to each line for convenience. */
		static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
		{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
		{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
		{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
		{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
		{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
		@@ -76,7 +76,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
		};

		static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
		{RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
		{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
		{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
		{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
		{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */

drivers/gpu/drm/i915/i915_reg.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -2637,7 +2637,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
		GEN9_STATE_ACK_TDL1 \| GEN9_STATE_ACK_TDL0)

		#define GFX_MODE _MMIO(0x2520)
		#define GFX_MODE_GEN7 _MMIO(0x229c)
		#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
		#define GFX_RUN_LIST_ENABLE (1 << 15)
		#define GFX_INTERRUPT_STEERING (1 << 14)